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Commission Asic Soc Design Engineer Jobs (NOW HIRING)

Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Knowledgeable about the ASIC design flow, including System Verilog RTL implementation. Preferred ...

As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software ...

SoC Design Engineer

Austin, TX · On-site

$122K - $232K/yr

The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...

We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop ...

We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop ...

Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

We are seeking an experienced Physical Design Engineer / Lead with 10+ years of experience in ASIC/SoC physical design. The ideal candidate will have hands-on expertise in the complete RTL-to-GDSII ...

This is a highly visible role, where you will be at the center of the ASIC design efforts ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...

Familiarity with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL languages like Verilog. Preferred Qualifications Shown experience writing micro-architecture ...

The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...

This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...

Familiarity with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL languages like Verilog. Preferred Qualifications MSEE with some years of industry experience Shown ...

This is a highly visible role, where you will be at the center of the ASIC design efforts ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...

We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ...

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How much do commission asic soc design engineer jobs pay per year?

As of Jul 20, 2026, the average yearly pay for commission asic soc design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
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Physical Design Engineer

Physical Design Engineer

Central Business Solutions

San Jose, CA • On-site, Remote

$159K - $164K/yr

Full-time

Re-posted 27 days ago


Job description

Title: Physical Design Engineer
Location: 100% Remote
Duration: Long Term Contract role

Responsibilities
  • Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
  • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
  • Deliver physical design of an end-to-end IP or integration of ASIC/SoC design

Minimum Qualifications:
  • Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design experience
  • Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies
  • Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge.
  • Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus, Calibre.

Preferred Qualification:
  • Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
  • Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
  • Experience in Block-level and Full-chip floor-planning, power grid planning
  • Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
  • Experience with Python, TCL, Perl programming.