As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software ...
As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software ...
Lead SoC Design Engineer
Los Altos, CA · On-site
We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop ...
Lead SoC Design Engineer
Los Altos, CA · On-site
We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop ...
Senior ASIC Design Engineer - Terawave
San Diego, CA · On-site
$230.40 - $322.56/hr
We are seeking a ASIC/SOC Design Validation engineers (all levels including Senior, Principal, Senior Principal) to work in the Design Validation team who are critical to ensuring our RFIC/ASIC ...
Senior ASIC Design Engineer - Terawave
San Diego, CA · On-site
$230.40 - $322.56/hr
We are seeking a ASIC/SOC Design Validation engineers (all levels including Senior, Principal, Senior Principal) to work in the Design Validation team who are critical to ensuring our RFIC/ASIC ...
Lead SoC Design Engineer
Los Altos, CA · On-site
We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop ...
Lead SoC Design Engineer
Los Altos, CA · On-site
We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop ...
Principal ASIC Design Engineer - Terawave
California, MO · On-site
$269.17 - $376.84/hr
We are seeking ASIC/SOC Design engineers who are critical to ensuring our RFIC/ASIC designs culminate in thoroughly designed and validated cutting‑edge integrated circuits that drive Blue Origin ...
Principal ASIC Design Engineer - Terawave
California, MO · On-site
$269.17 - $376.84/hr
We are seeking ASIC/SOC Design engineers who are critical to ensuring our RFIC/ASIC designs culminate in thoroughly designed and validated cutting‑edge integrated circuits that drive Blue Origin ...
SoC Design Engineer
Austin, TX · On-site
$122K - $232K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
SoC Design Engineer
Austin, TX · On-site
$122K - $232K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
ASIC Design Engineer
Beaverton, OR · On-site
$150 - $210/hr
Integrate complex IPs into the SOC * Support all front end integration activities like Lint, CDC, Synthesis, and ECO * Work with other specialists that are members of the SOC Design, SOC Design ...
ASIC Design Engineer
Beaverton, OR · On-site
$150 - $210/hr
Integrate complex IPs into the SOC * Support all front end integration activities like Lint, CDC, Synthesis, and ECO * Work with other specialists that are members of the SOC Design, SOC Design ...
Senior FPGA Design Engineer
Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation with Altera Quartus or Xilinx Vivado * Experience designing/debugging SoC systems with AMBA-compliant ...
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Senior FPGA Design Engineer
Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation with Altera Quartus or Xilinx Vivado * Experience designing/debugging SoC systems with AMBA-compliant ...
TPU SoC Integration Engineer, Cloud
Sunnyvale, CA · On-site
$163 - $236/hr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related ... of experience in ASIC design or RTL design. * Experience with SoC design and integration.
TPU SoC Integration Engineer, Cloud
Sunnyvale, CA · On-site
$163 - $236/hr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related ... of experience in ASIC design or RTL design. * Experience with SoC design and integration.
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
Principal ASIC Design Engineer - Terawave
San Diego, CA · On-site
$269K - $376K/yr
We are seeking ASIC/SOC Design engineers who are critical to ensuring our RFIC/ASIC designs culminate in thoroughly designed and validated cutting-edge integrated circuits that drive Blue Origin ...
Principal ASIC Design Engineer - Terawave
San Diego, CA · On-site
$269K - $376K/yr
We are seeking ASIC/SOC Design engineers who are critical to ensuring our RFIC/ASIC designs culminate in thoroughly designed and validated cutting-edge integrated circuits that drive Blue Origin ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Knowledge of digital design, SoC architecture, and HDL languages like Verilog. Familiarity with ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Knowledge of digital design, SoC architecture, and HDL languages like Verilog. Familiarity with ...
Wireless SoC Design Engineer
$122K - $214K/yr
This is a highly visible role, where you will be at the center of the ASIC design efforts ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...
Wireless SoC Design Engineer
$122K - $214K/yr
This is a highly visible role, where you will be at the center of the ASIC design efforts ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...
Familiarity with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL languages like Verilog. Preferred Qualifications Shown experience writing micro-architecture ...
Familiarity with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL languages like Verilog. Preferred Qualifications Shown experience writing micro-architecture ...
SoC Design Engineer
$122K - $232K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
SoC Design Engineer
$122K - $232K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Wireless SoC Design Engineer
$175K - $308K/yr
This is a highly visible role, where you will be at the center of the ASIC design efforts ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...
Wireless SoC Design Engineer
$175K - $308K/yr
This is a highly visible role, where you will be at the center of the ASIC design efforts ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...
Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. * Build and maintain infrastructure/environment for automation ...
Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. * Build and maintain infrastructure/environment for automation ...
PCIe ASIC Design Engineer
San Jose, CA · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ...
PCIe ASIC Design Engineer
San Jose, CA · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ...
Wireless SoC Design Engineer
$122K - $214K/yr
This is a highly visible role, where you will be at the center of the ASIC design efforts ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...
Wireless SoC Design Engineer
$122K - $214K/yr
This is a highly visible role, where you will be at the center of the ASIC design efforts ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...
Commission Asic Soc Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do commission asic soc design engineer jobs pay per year?
Nvidia rating
9.6
Based on 17 frontline employees who took The Breakroom Quiz
8th of 242 rated software companies
Job description
From pioneering the GPU in 1999-sparking the PC gaming revolution and redefining computer graphics-to leading the charge in AI and deep learning, we are always pushing boundaries." We're a "learning machine," constantly evolving to solve new challenges and seize opportunities that make a real difference. If you're driven by innovation and want to be part of a team that's shaping the future, NVIDIA is where your impact will be felt!
What you'll be doing:
- Integrate diverse IP blocks to build NVIDIA's next-generation GPUs and SOCs
- Develop and refine system-level methodologies and tools for efficient SOC creation
- Streamline SOC design and assembly through innovative integration efforts
- Spot inefficiencies in the front-end chip implementation process and propose actionable improvements
- Ensure high-quality RTL delivery to the physical design team with thorough design quality checks and reviews
- Collaborate across teams to drive standard methodologies and continuous improvement in SOC development
What we need to see:
- BS or MS in Computer Engineering, Electrical Engineering, or equivalent experience
- 3+ years of hands-on chip design experience, with a focus on SOC integration and automation
- Strong analytical and problem-solving skills
- Expertise in RTL design, SOC integration, and design automation flows
- Proficiency in Perl, Python, or similar scripting languages
- Excellent communication and teamwork abilities to build consensus within and across teams
- Experience in synthesis, padring, and physical design is a plus
Ways to stand out from the crowd:
- Led SOC automation initiatives that significantly boosted efficiency or quality
- Hands-on expertise with industry-standard EDA tools and flows, especially for large-scale SOC integration
- Experience mentoring junior engineers or leading cross-functional technical projects
NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most brilliant and talented people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the most sophisticated chips in the world? If so, we want to hear from you.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until July 28, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993