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Commission Asic Soc Design Engineer Jobs (NOW HIRING)

SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...

Familiarity with ASIC low power design techniques, including multiple supply domains configuration ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...

Preferred Qualifications Skilled in defining ASIC microarchitecture to meet functional requirements ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...

Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified ... Skilled in defining ASIC microarchitecture to meet functional requirements while managing ...

As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software ...

SoC Design Engineer

Austin, TX · On-site

$122K - $232K/yr

The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...

All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...

SoC Design Engineer

Austin, TX · On-site

$122K - $232K/yr

The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...

All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...

All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...

Debug SoC Design Engineer

Irvine, CA · On-site

$146K - $178K/yr

This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Knowledge of digital design, SoC architecture, and HDL languages like Verilog.Familiarity with ...

This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...

This is a highly visible role, where you will be at the center of the ASIC design efforts ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...

This is a highly visible role, where you will be at the center of the ASIC design efforts ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...

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Commission Asic Soc Design Engineer information

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$150.2K

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How much do commission asic soc design engineer jobs pay per year?

As of Jun 21, 2026, the average yearly pay for commission asic soc design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
What cities are hiring for Commission Asic Soc Design Engineer jobs? Cities with the most Commission Asic Soc Design Engineer job openings:
What are the most commonly searched types of Asic Soc Design Engineer jobs? The most popular types of Asic Soc Design Engineer jobs are:
What states have the most Commission Asic Soc Design Engineer jobs? States with the most job openings for Commission Asic Soc Design Engineer jobs include:
SoC Design Engineer

$156K - $160K/yr

Full-time

Posted 14 days ago


Job description

Job Title: SoC Design Engineer
 
Job Duties:
 
  • Design and verify digital circuits for CMOS image sensors (CIS), including sensor array timing control logic, analog-digital interface modules, and ISP (Image Signal Processing) data pipelines, in accordance with product requirements, system architecture, and ASIC design methodology.
  • Perform full-chip SoC integration, including IP integration, clock/reset domain management, power-aware design, and system-level verification to ensure functional correctness and tape-out readiness.
  • Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog/SystemVerilog, simulation, synthesis and DFT implementation.
  • Conduct static timing analysis (STA) for image sensor timing-critical paths, including interfaces between analog front-end and digital control logic, ensuring robust timing closure across process corners.
  • Collaborate closely with the back-end physical design team on floor planning, timing closure, power optimization, and DFT strategy throughout the implementation cycle.
  • Perform pre-silicon verification using UVM-based testbenches, and scripting languages (Python, Perl) for automation, coverage analysis, and regression testing.
  • Work with sensor analog/digital engineers to co-develop system-level architectures, define interface protocols, and validate mixed-signal functionality during integration and bring-up.
  • Partner with algorithm engineers to implement hardware-efficient microarchitectures, develop C/C++ reference models, perform RTL-to-model co-simulation, and optimize hardware/software partitioning for imaging pipelines.
  • Support post-silicon activities including chip bring-up, silicon validation, debugging, and performance tuning in collaboration with firmware, application, and image quality teams.
  • Contribute to image tuning, sensor characterization, and product qualification by analyzing hardware behavior and providing feedback to algorithm and system teams.
  • Create and maintain technical documentation, including architecture specifications, registers, interface control documents. 
 
Requirements:
 
Master’s degree or foreign equivalent degree in Electrical Engineering, Computer Engineering, or a closely related field
 
Require one year experience in digital design.
 
Must have the experience/skills:
 
  • Architecture for Wi-Fi 6 AP transmitter.
  • Wi-Fi PHY based RTL design and verification using Verilog.
  • Module-level verification and full-chip integration support.
  • Design optimization techniques for area, power, and timing.
  • Using industry-standard digital design and verification tools.
 

Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.