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Commission Asic Soc Design Engineer Jobs (NOW HIRING)

Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...

Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...

Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...

Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ... Skilled in defining ASIC microarchitecture to meet functional requirements while managing ...

Familiarity with ASIC low power design techniques, including multiple supply domains configuration ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...

Preferred Qualifications Skilled in defining ASIC microarchitecture to meet functional requirements ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...

SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...

Familiarity with ASIC low power design techniques, including multiple supply domains configuration ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...

Preferred Qualifications Skilled in defining ASIC microarchitecture to meet functional requirements ... Additionally, this role might be eligible for discretionary bonuses or commission payments as well ...

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Commission Asic Soc Design Engineer information

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$94K

$150.2K

$202K

How much do commission asic soc design engineer jobs pay per year?

As of Jul 20, 2026, the average yearly pay for commission asic soc design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
What cities are hiring for Commission Asic Soc Design Engineer jobs? Cities with the most Commission Asic Soc Design Engineer job openings:
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What states have the most Commission Asic Soc Design Engineer jobs? States with the most job openings for Commission Asic Soc Design Engineer jobs include:
ASIC RTL/SoC Design Engineer

ASIC RTL/SoC Design Engineer

TetraMem INC

Fremont, CA

Full-time

Medical, Retirement, PTO

Posted 11 days ago


Job description

Company Description

TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware.

We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, and other perks.

Job Description
  • Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs.

  • Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility.

  • Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs.

  • Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout.

  • Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications.

  • Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product.

  • Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth.

  • Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability.

  • Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency.

  • Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery.

Qualifications
  • MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design

  • Experience with Verilog and system Verilog

  • Experience with VCS, Verdi or other industry standard tools

  • Experience with pre-layout simulation and post-layout simulation

  • Understanding of the design flow. Ability to work with the backend team

  • Familiarity with AMBA APB AXI Protocol

  • Familiarity with RISC/Arm or other core architectures

  • Ability to create innovative architecture and solutions to customer requirements

  • Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.

Experience in one or more of the following areas considered a strong plus:

  • FPGA/ASIC design of image processing systems

  • Working knowledge of SoC architecture such as CPU, GPU or accelerators

  • Familiarity with: UVM, place-and-route, STA, EM/IR/Power

Additional Information

All your information will be kept confidential according to EEO guidelines.