... chip designs described in C++, Verilog or domain-specific languages (DSLs). • Research and develop software solutions to allow greater efficiency in architecture, hardware and software teams. • ...
... chip designs described in C++, Verilog or domain-specific languages (DSLs). • Research and develop software solutions to allow greater efficiency in architecture, hardware and software teams. • ...
Chip Design and Verification Methodology Engineer
San Francisco, CA · On-site
$150 - $190/hr
Chip Design and Verification Methodology Engineer San Francisco Bay Area, CA · Hybrid · Full-time ... You will define what "done" means for AI-generated designs. * Deep-Dive Debugging : Go beyond pass ...
Chip Design and Verification Methodology Engineer
San Francisco, CA · On-site
$150 - $190/hr
Chip Design and Verification Methodology Engineer San Francisco Bay Area, CA · Hybrid · Full-time ... You will define what "done" means for AI-generated designs. * Deep-Dive Debugging : Go beyond pass ...
Senior C++ Software Engineer - Chip Design Tools
Santa Clara, CA · On-site
$152 - $241.50/hr
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Senior C++ Software Engineer - Chip Design Tools
Santa Clara, CA · On-site
$152 - $241.50/hr
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs). * Research and develop software solutions to allow greater ...
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs * Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance * Drive tapeout ...
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs * Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance * Drive tapeout ...
UX / Interaction Designer
California, MO · On-site
$80 - $120/hr
We combine machine learning, large language models (LLMs), and deep domain knowledge in chip design ... About the role We're hiring a UX / Interaction Designer to define and craft the next generation of ...
UX / Interaction Designer
California, MO · On-site
$80 - $120/hr
We combine machine learning, large language models (LLMs), and deep domain knowledge in chip design ... About the role We're hiring a UX / Interaction Designer to define and craft the next generation of ...
Principal Layout Designer, Next-generation HBM Architecture
Richardson, TX · On-site
$100.56 - $168.07/hr
Integrate full chip designs and perform layout verification (LVS, DRC), quality checks, and documentation. * Collaborate and communicate across domains, including signal integrity, architecture ...
Principal Layout Designer, Next-generation HBM Architecture
Richardson, TX · On-site
$100.56 - $168.07/hr
Integrate full chip designs and perform layout verification (LVS, DRC), quality checks, and documentation. * Collaborate and communicate across domains, including signal integrity, architecture ...
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs * Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance * Drive tapeout ...
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs * Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance * Drive tapeout ...
NoC Architect (Network on Chip)
San Francisco, CA · On-site
$180 - $230/hr
Hands on experience in designing, integrating, verifying NoCs * Decided on build vs buy for NoC IP and justified it * Experience in verification of NoCs, especially for NoC and IP integration Nice to ...
NoC Architect (Network on Chip)
San Francisco, CA · On-site
$180 - $230/hr
Hands on experience in designing, integrating, verifying NoCs * Decided on build vs buy for NoC IP and justified it * Experience in verification of NoCs, especially for NoC and IP integration Nice to ...
Principal Layout Designer, Next-generation HBM Architecture
Richardson, TX · On-site
$85.75 - $168.07/hr
Integrate full chip designs and perform layout verification (LVS, DRC), quality checks, and documentation. * Collaborate and communicate across domains--signal integrity, architecture, design, and ...
Principal Layout Designer, Next-generation HBM Architecture
Richardson, TX · On-site
$85.75 - $168.07/hr
Integrate full chip designs and perform layout verification (LVS, DRC), quality checks, and documentation. * Collaborate and communicate across domains--signal integrity, architecture, design, and ...
NoC Architect (Network on Chip)
Boston, MA · On-site
$180 - $230/hr
Hands on experience in designing, integrating, verifying NoCs * Decided on build vs buy for NoC IP and justified it * Experience in verification of NoCs, especially for NoC and IP integration Nice to ...
NoC Architect (Network on Chip)
Boston, MA · On-site
$180 - $230/hr
Hands on experience in designing, integrating, verifying NoCs * Decided on build vs buy for NoC IP and justified it * Experience in verification of NoCs, especially for NoC and IP integration Nice to ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs * Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance * Drive tapeout ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs * Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance * Drive tapeout ...
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs * Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance * Drive tapeout ...
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs * Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance * Drive tapeout ...
NoC Architect (Network on Chip)
Austin, TX · On-site
$180 - $230/hr
Hands on experience in designing, integrating, verifying NoCs * Decided on build vs buy for NoC IP and justified it * Experience in verification of NoCs, especially for NoC and IP integration Nice to ...
NoC Architect (Network on Chip)
Austin, TX · On-site
$180 - $230/hr
Hands on experience in designing, integrating, verifying NoCs * Decided on build vs buy for NoC IP and justified it * Experience in verification of NoCs, especially for NoC and IP integration Nice to ...
ASIC Chip Design Lead
Saratoga, CA · On-site
$250K - $280K/yr
Review checklist status with designers and proactively push closure of open items * Continuously ... Proven experience with full-chip integration and timing closure * Led at least one full-chip tape ...
ASIC Chip Design Lead
Saratoga, CA · On-site
$250K - $280K/yr
Review checklist status with designers and proactively push closure of open items * Continuously ... Proven experience with full-chip integration and timing closure * Led at least one full-chip tape ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$175K - $280K/yr
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs * Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance * Drive tapeout ...
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$175K - $280K/yr
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs * Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance * Drive tapeout ...
Chip Designer information
See salary details
$21.5K - $29.7K
9% of jobs
$29.7K - $38K
1% of jobs
$44.2K is the 25th percentile. Wages below this are outliers.
$38K - $46.2K
20% of jobs
$46.2K - $54.4K
12% of jobs
The median wage is $60.4K / yr.
$54.4K - $62.6K
12% of jobs
$62.6K - $70.9K
17% of jobs
$76.2K is the 75th percentile. Wages above this are outliers.
$70.9K - $79.1K
7% of jobs
$79.1K - $87.3K
4% of jobs
$87.3K - $95.5K
7% of jobs
$95.5K - $103.8K
4% of jobs
$103.8K - $112K
6% of jobs
$21.5K
$65.4K
$112K
How much do chip designer jobs pay per year?
What is a chip designer?
What are some common challenges chip designers face when working on complex integrated circuits?
What are the key skills and qualifications needed to thrive as a chip designer, and why are they important?
What is the difference between Chip Designer vs ASIC Designer?
| Aspect | Chip Designer | ASIC Designer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering | Bachelor's or Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Design labs, offices, CAD software | Design labs, offices, CAD software |
| Industry Usage | Broadly used in various electronics sectors | Primarily in custom chip development for specific applications |
| Comparison Focus | General chip design processes | Designing specific Application-Specific Integrated Circuits |
While both roles involve designing integrated circuits, a Chip Designer focuses on creating general-purpose chips, whereas an ASIC Designer specializes in designing custom chips for specific applications. The skills and work environments overlap significantly, but their project scopes differ.
Are chip designers in demand?
How hard is it to get into chip design?
How much do chip designers make?
What cities are hiring for Chip Designer jobs?
Cities with the most Chip Designer job openings:
What job categories do people searching Chip Designer jobs look for?
The top searched job categories for Chip Designer jobs are:

Full-time
Re-posted 18 days ago
Nvidia rating
9.6
Based on 17 frontline employees who took The Breakroom Quiz
7th of 246 rated software companies
Job description
NVIDIA is a leading technology company known for its innovative contributions to the GPU market and AI. They are seeking a Senior C++ Software Engineer to develop and support infrastructure tools for chip design and verification processes, ensuring high performance and reliability for design engineers.
Responsibilities:
• Work as a team to build reliable, scalable and high performance software that are easy to use by hundreds of engineers worldwide.
• Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs).
• Research and develop software solutions to allow greater efficiency in architecture, hardware and software teams.
• Optimize the daily workflows of the world's top chip modelers and designers.
Qualifications:
Required:
• BS (or equivalent experience) and 5+ years of software development experience.
• Experienced with C++ or Golang, Unix/Linux.
• Solid understanding of algorithms, computer architecture and computer science theory
• Experienced with VLSI frontend design and verification
• Flexibility/adaptability for working in a global and dynamic environment with different frameworks and requirements
Preferred:
• MS (or PHD) preferred.
• Good architecture and RTL design knowledge
• Strong expertise in modern C++, compiler, build systems, and database.
• Experienced with static and dynamic code analysis tools
Company:
NVIDIA is a computing platform company operating at the intersection of graphics, HPC, and AI. Founded in 1993, the company is headquartered in Santa Clara, USA, with a team of 10001+ employees. The company is currently Late Stage.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993