Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to ... every stage - from internship to retirement and through life's most important moments. Our ...
Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to ... every stage - from internship to retirement and through life's most important moments. Our ...
Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to ... every stage - from internship to retirement and through life's most important moments. Our ...
Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to ... every stage - from internship to retirement and through life's most important moments. Our ...
Software Engineer, ASIC
South San Francisco, CA · On-site
$123K - $216K/yr
As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span ... Temporary Employees & Interns excluded
Software Engineer, ASIC
South San Francisco, CA · On-site
$123K - $216K/yr
As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span ... Temporary Employees & Interns excluded
You will work closely with ASIC Design, Applications and Test Engineering teams to design, develop ... every stage - from internship to retirement and through life's most important moments. Our ...
You will work closely with ASIC Design, Applications and Test Engineering teams to design, develop ... every stage - from internship to retirement and through life's most important moments. Our ...
ASIC Architect
Santa Clara, CA · On-site
What You Can Expect The ASIC Architect serves as a senior technical leader within the company ... every stage - from internship to retirement and through life's most important moments. Our ...
ASIC Architect
Santa Clara, CA · On-site
What You Can Expect The ASIC Architect serves as a senior technical leader within the company ... every stage - from internship to retirement and through life's most important moments. Our ...
You will work closely with ASIC Design, Applications and Test Engineering teams to design, develop ... every stage - from internship to retirement and through life's most important moments. Our ...
You will work closely with ASIC Design, Applications and Test Engineering teams to design, develop ... every stage - from internship to retirement and through life's most important moments. Our ...
ASIC Design Intern
Beaverton, OR · On-site
We are seeking a motivated ASIC Design Intern (Co-op or Internship) to join our engineering team during the summer term. This role is designed for students who are eager to gain hands-on experience ...
ASIC Design Intern
Beaverton, OR · On-site
We are seeking a motivated ASIC Design Intern (Co-op or Internship) to join our engineering team during the summer term. This role is designed for students who are eager to gain hands-on experience ...
ASIC Security Architect
Santa Clara, CA · On-site
$76.25 - $98.75/hr
The ASIC Security Architect serves as a senior technical leader within the company, guiding the ... every stage - from internship to retirement and through life's most important moments. Our ...
ASIC Security Architect
Santa Clara, CA · On-site
$76.25 - $98.75/hr
The ASIC Security Architect serves as a senior technical leader within the company, guiding the ... every stage - from internship to retirement and through life's most important moments. Our ...
ASIC Security Architect
Santa Clara, CA · On-site
$76.25 - $98.75/hr
The ASIC Security Architect serves as a senior technical leader within the company, guiding the ... every stage - from internship to retirement and through life's most important moments. Our ...
ASIC Security Architect
Santa Clara, CA · On-site
$76.25 - $98.75/hr
The ASIC Security Architect serves as a senior technical leader within the company, guiding the ... every stage - from internship to retirement and through life's most important moments. Our ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you ... Show leadership and provide guidance to new college-grad/juniorengineers and interns. Recommended ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you ... Show leadership and provide guidance to new college-grad/juniorengineers and interns. Recommended ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you ... Show leadership and provide guidance to new college-grad/juniorengineers and interns. Recommended ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you ... Show leadership and provide guidance to new college-grad/juniorengineers and interns. Recommended ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you ... Show leadership and provide guidance to new college-grad/juniorengineers and interns. Recommended ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you ... Show leadership and provide guidance to new college-grad/juniorengineers and interns. Recommended ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you ... Show leadership and provide guidance to new college-grad/junior engineers and interns. Recommended ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you ... Show leadership and provide guidance to new college-grad/junior engineers and interns. Recommended ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... interns. Recommended skills • Bachelor's degree in electrical engineering required (Master ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... interns. Recommended skills • Bachelor's degree in electrical engineering required (Master ...
We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect ... A history of mentoring junior engineers and interns a huge plus. NVIDIA is widely considered to be ...
We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect ... A history of mentoring junior engineers and interns a huge plus. NVIDIA is widely considered to be ...
We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect ... A history of mentoring junior engineers and interns a huge plus. NVIDIA is widely considered to be ...
We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect ... A history of mentoring junior engineers and interns a huge plus. NVIDIA is widely considered to be ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... and interns. Recommended skills Bachelor's degree in electrical engineering required (Master ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... and interns. Recommended skills Bachelor's degree in electrical engineering required (Master ...
We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect ... A history of mentoring junior engineers and interns a huge plus. NVIDIA is widely considered to be ...
We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect ... A history of mentoring junior engineers and interns a huge plus. NVIDIA is widely considered to be ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... and interns. Recommended skills Bachelor's degree in electrical engineering required (Master ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... and interns. Recommended skills Bachelor's degree in electrical engineering required (Master ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... and interns. Recommended skills Bachelor's degree in electrical engineering required (Master ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... and interns. Recommended skills Bachelor's degree in electrical engineering required (Master ...
Asic Internships information
See salary details
$12.98 - $15.97
3% of jobs
$15.97 - $18.97
13% of jobs
$20.38 is the 25th percentile. Wages below this are outliers.
$18.97 - $21.96
19% of jobs
$21.96 - $24.96
13% of jobs
The median wage is $25.50 / hr.
$24.96 - $27.95
12% of jobs
$27.95 - $30.94
6% of jobs
$30.94 - $33.94
6% of jobs
$34.87 is the 75th percentile. Wages above this are outliers.
$33.94 - $36.93
9% of jobs
$36.93 - $39.93
10% of jobs
$39.93 - $42.92
4% of jobs
$42.92 - $45.91
5% of jobs
$12
$28
$45
How much do asic internships jobs pay per hour?
What are the key skills and qualifications needed to thrive as an ASIC Intern, and why are they important?
What types of projects do ASIC interns typically work on, and how do these assignments support their professional development?
What are ASIC internships?
What is the difference between Asic Internships vs ASIC Design Engineer?
| Aspect | Asic Internships | ASIC Design Engineer |
|---|---|---|
| Required Credentials | Typically pursuing or recent graduates in Electrical Engineering or Computer Engineering | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields |
| Work Environment | Internship programs in tech companies, labs, or research institutions | Full-time professional roles in design teams, R&D departments, or semiconductor companies |
| Employer & Industry Usage | Used by companies to train and evaluate potential future employees | Established role responsible for designing and developing ASIC chips |
Asic Internships are temporary training positions aimed at gaining industry experience, while ASIC Design Engineers are full-time professionals responsible for designing integrated circuits. Internships often serve as a stepping stone to a career as an ASIC Design Engineer, providing practical skills and industry exposure.

Full-time
Life, Retirement
Posted 12 days ago
Job description
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system's interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI's Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.
The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.
What You Can Expect
We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to-end design and development of high-performance ASICs, ensuring technical excellence, on-time project delivery, and alignment with company goals.
This role demands proven technical expertise in advanced ASIC design flows and leadership in execution, scheduling, cross-functional coordination, and final product delivery.
What We're Looking For
- Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree
- 8+ years of ASIC/SOC digital design experience
- 3+ years of people management experience
- Excellent leadership, communication, team building and stakeholder management skills
- Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints
- Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies
- Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies
- Hands on design experience in one or more industry standards/protocol stacks such as CXL, PCIe, HBM, UCIe, UALink etc
- Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory)
- Proficiency with front end development tools/methodologies, and scripting for automation and flow integration
Expected Base Pay Range (USD)
161,600 - 239,210, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
#LI-VM1
About Marvell
Sourced by ZipRecruiter
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1995