Austin, TX · On-site
$134K - $138K/yr
Logic Design, VLSI/ASIC Design, Computer Architecture Current Industry Experience in one or more ASIC style design flows - floorplanning, clock construction, synthesis, place and route, static timing ...
Austin, TX · On-site
$134K - $138K/yr
Logic Design, VLSI/ASIC Design, Computer Architecture Current Industry Experience in one or more ASIC style design flows - floorplanning, clock construction, synthesis, place and route, static timing ...
$129K - $194K/yr
Preferred Qualifications Experience with ASIC or AMS physical implementation and analysis flow ... Scripting skills to automate and debug verification flows for digital VLSI design. Circuit design ...
$129K - $194K/yr
Preferred Qualifications Experience with ASIC or AMS physical implementation and analysis flow ... Scripting skills to automate and debug verification flows for digital VLSI design. Circuit design ...
$184K - $324K/yr
Experience with ASIC or AMS physical implementation and analysis flow for IP blocks as well as SoC fullchip. Proficient in automating and debugging verification flows for digital VLSI design.
$184K - $324K/yr
Experience with ASIC or AMS physical implementation and analysis flow for IP blocks as well as SoC fullchip. Proficient in automating and debugging verification flows for digital VLSI design.
$184K - $324K/yr
Experience with ASIC or AMS physical implementation and analysis flow for IP blocks as well as SoC fullchip. Proficient in automating and debugging verification flows for digital VLSI design.
$184K - $324K/yr
Experience with ASIC or AMS physical implementation and analysis flow for IP blocks as well as SoC fullchip. Proficient in automating and debugging verification flows for digital VLSI design.
Austin, TX · On-site
$103K - $142K/yr
An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can ... Strong background of VLSI, digital design, and computer architecture concepts. * Good understanding ...
Austin, TX · On-site
$103K - $142K/yr
An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can ... Strong background of VLSI, digital design, and computer architecture concepts. * Good understanding ...
Austin, TX · On-site
$103K - $142K/yr
An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can ... Strong background of VLSI, digital design, and computer architecture concepts. * Good understanding ...
Austin, TX · On-site
$103K - $142K/yr
An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can ... Strong background of VLSI, digital design, and computer architecture concepts. * Good understanding ...
An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can ... Understanding of VLSI, digital design, and computer architecture concepts. * Basic understanding of ...
An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can ... Understanding of VLSI, digital design, and computer architecture concepts. * Basic understanding of ...
An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can ... Understanding of VLSI, digital design, and computer architecture concepts. * Basic understanding of ...
An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can ... Understanding of VLSI, digital design, and computer architecture concepts. * Basic understanding of ...
$175K - $311K/yr
... in ASIC/SOC/VLSI Designs or similar experience Strong knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Pay & Benefits ...
$175K - $311K/yr
... in ASIC/SOC/VLSI Designs or similar experience Strong knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Pay & Benefits ...
Austin, TX · Hybrid
$110K - $130K/yr
Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow environments. * Hands-on experience with EDA tools. * Experienced in UNIX Systems programming and automation using Python and/or ...
Austin, TX · Hybrid
$110K - $130K/yr
Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow environments. * Hands-on experience with EDA tools. * Experienced in UNIX Systems programming and automation using Python and/or ...
$175K - $311K/yr
... in ASIC/SOC/VLSI Designs or similar experience Strong knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Pay & Benefits ...
$175K - $311K/yr
... in ASIC/SOC/VLSI Designs or similar experience Strong knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Pay & Benefits ...
$144K - $263K/yr
... in ASIC/SOC/VLSI Designs or similar experience Good knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Pay & Benefits At ...
$144K - $263K/yr
... in ASIC/SOC/VLSI Designs or similar experience Good knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Pay & Benefits At ...
$175K - $311K/yr
... in ASIC/SOC/VLSI Designs or similar experience Strong knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Pay & Benefits ...
$175K - $311K/yr
... in ASIC/SOC/VLSI Designs or similar experience Strong knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Pay & Benefits ...
$144K - $263K/yr
... in ASIC/SOC/VLSI Designs or similar experience Good knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Pay & Benefits At ...
$144K - $263K/yr
... in ASIC/SOC/VLSI Designs or similar experience Good knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Pay & Benefits At ...
Austin, TX · On-site
$120 - $180/hr
... in ASIC/SOC/VLSI Designs or similar experience * Strong knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Preferred ...
Austin, TX · On-site
$120 - $180/hr
... in ASIC/SOC/VLSI Designs or similar experience * Strong knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Preferred ...
$144K - $263K/yr
... in ASIC/SOC/VLSI Designs or similar experience Good knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Pay & Benefits At ...
$144K - $263K/yr
... in ASIC/SOC/VLSI Designs or similar experience Good knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOC Pay & Benefits At ...
| Aspect | Asic In Vlsi | FPGA Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's/Master's in Electrical Engineering or VLSI Design, certifications like Cadence or Synopsys tools | Bachelor's/Master's in Electrical Engineering or VLSI Design, similar certifications |
| Work Environment | Designing and developing custom integrated circuits in a semiconductor fabrication environment | Developing and testing FPGA-based solutions, often in prototyping or embedded systems |
| Industry Usage | Used in high-volume chip manufacturing, consumer electronics, and specialized hardware | Used in rapid prototyping, embedded systems, and applications requiring flexible hardware |
While both roles involve VLSI design skills and similar educational backgrounds, Asic In Vlsi focuses on designing custom chips for manufacturing, whereas FPGA Design Engineers work on programmable hardware solutions. The choice depends on whether you prefer working on fixed, high-volume chips or flexible, reconfigurable hardware.
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$134K - $138K/yr
Full-time
Medical, Retirement, PTO
Re-posted 6 days ago
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 159 rated electronics manufacturers
At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers.
The Physical Design Integration Engineer performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, lowpower synthesizable CPU. Optimizes CPU design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.
Responsibilities
The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc
Responsibilities may also include defining design requirements such as frequency, operating voltages, power, etc. to achieve optimized designs on new technologies, processes and architectures
The candidate would be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle and take the key learnings into the next product cycle
We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems
Good leadership and communication skills are necessary due to the nature of the work, size and complexity of the products and the size of the team
Qualifications:A successful candidate will have proven experience demonstrating the following skills and behavioral traits:
Bachelor's in Electrical/Computer Engineering with 15+ years relevant work experience, or Master's in Electrical/Computer Engineering with 12+ years relevant work experience
The ideal candidate will be capable of leading a small team as well as interacting with architecture and design teams to improve IP and ultimate product quality and performance
Experience in: Logic Design, VLSI/ASIC Design, Computer Architecture
Current Industry Experience in one or more ASIC style design flows - floorplanning, clock construction, synthesis, place and route, static timing analysis, layout verification
Experience with Unix/Linux, Perl and TCL in order to implement useable, flexible cshell/perl/tcl programs that automate tool/flow methodologies
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $256,050.00-361,480.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Manufacturing
10,000+ Employees
Santa Clara, CA, US
1968
