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Asic Engineering Jobs in Colorado (NOW HIRING)

Broadcom's ASIC Products Division is seeking a Design Automation Software Development Engineer in the Design For Test (DFT) team developing SoC ASIC products. They will define, develop, deploy and ...

We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market ...

Senior FPGA Engineer

Englewood, CO · On-site

$130K - $185K/yr

Company Description Join SEAKR Engineering, a leading-edge provider of advanced electronics for ... Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of ...

IP Integration Engineer

Fort Collins, CO · On-site

$102K - $138K/yr

... Engineering and 12+ years of related experience; or Masters degree and 10+ years of related experience * Understanding of design trade offs for power, area, and speed in ASIC designs. * Have an ...

Senior FPGA Engineer

Englewood, CO · On-site

$130K - $185K/yr

Company Description Join SEAKR Engineering, a leading-edge provider of advanced electronics for ... Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of ...

Verification Engineer

Englewood, CO · On-site

$130K - $200K/yr

Work on both ASIC and FPGA Space system projects Job Qualifications: * 7+ years of relevant design ... Protingent is an Award-Winning provider of top-tier Engineering and IT talent, trusted by companies ...

IP Integration Engineer

Fort Collins, CO · On-site

$102K - $138K/yr

... Engineering and 12+ years of related experience; or Masters degree and 10+ years of related experience * Understanding of design trade offs for power, area, and speed in ASIC designs. * Have an ...

Design Verification Engineer

Fort Collins, CO · On-site

$134K - $164K/yr

Bachelor's Degree in Electrical and Electronic Engineering, Computer Science, or a related field. * Experience: 17+ years of relevant industry experience in ASIC design verification (preferred)

Design Verification Engineer

Broomfield, CO · On-site

$108 - $172.80/hr

Design Verification Engineer Broadcom's ASIC Products Division (APD) is looking for an experienced verification engineer responsible for modeling and verification activities for complex digital and ...

Showing results 21-40

Asic Engineering information

What is the difference between Asic Engineering vs FPGA Design?

AspectAsic EngineeringFPGA Design
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; often certifications in ASIC designBachelor's or Master's in Electrical Engineering, Digital Design, or related fields; certifications less common
Work EnvironmentDesigning custom chips in semiconductor labs or design houses; involves hardware and software integrationDeveloping programmable logic designs in labs or FPGA development environments; focuses on reconfigurable hardware
Industry UsageUsed in high-volume consumer electronics, telecom, and automotive industries for custom chip solutionsCommon in prototyping, testing, and specialized applications across various industries

Asic Engineering and FPGA Design share foundational knowledge in digital logic and hardware description languages. However, Asic Engineers focus on designing permanent, high-volume chips, while FPGA Designers work with reconfigurable hardware for testing and specialized tasks. Both roles require similar educational backgrounds but differ in application and design processes.

What are popular job titles related to Asic Engineering jobs in Colorado? For Asic Engineering jobs in Colorado, the most frequently searched job titles are:
What job categories do people searching Asic Engineering jobs in Colorado look for? The top searched job categories for Asic Engineering jobs in Colorado are:

ASIC Digital Physical Design Manager

Keysight Technologies, Inc.

Colorado Springs, CO • On-site

$134K - $138K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 11 days ago


Keysight Technologies rating

8.1

Company rating: 8.1 out of 10

Based on 20 frontline employees who took The Breakroom Quiz

49th of 156 rated electronics manufacturers


Job description

Overview

Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.

Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.

This role sits within Keysight Laboratories—a globally recognized technology organization that enables Keysight to be first to market with breakthrough, highly differentiated solutions. Our team of senior engineers has delivered generations of innovation across ASIC and product development, spanning the breadth of the technology landscape. You’ll join a high-performance, globally connected engineering organization designing and delivering next-generation Digital and Mixed signal ASICs.

A sustained driver of Keysight’s success is the creation and deployment of breakthrough digital and mixed-signal ASICs that unlock step-function performance and customer value in new products. We are seeking an ASIC Physical Design R&D Manager to lead our ASIC Physical Design team—overseeing end-to-end physical implementation and ensuring designs meet aggressive performance, power, and area targets through tapeout and into product development.

The position is based in Colorado Springs at the foot of Pikes Peak, with a purpose-built development campus that brings engineering, advanced technology development, assembly, and machining together in one location. Outside the lab, the campus supports an active lifestyle with on-site fitness and recreation, and Colorado Springs offers exceptional quality of life—immediate access to world-class outdoor activities, year-round recreation, and more than 300 days of sunshine each year.


Responsibilities
  • Drive the physical design technical strategy across programs, including floorplanning, power architecture, and implementation trade-offs to meet PPA (performance, power, area) targets.
  • Lead, mentor, and grow a high-performing Physical Design team; set clear expectations for technical rigor, execution, and delivery.
  • Oversee physical implementation for digital, mixed-signal, and third-party IP—from block to subsystem to top-level integration—including place and route, timing closure, and power closure.
  • Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs, rapid issue resolution, and aligned delivery through tapeout.
  • Own and continuously improve the Physical Design flow, including methodology, automation, CI/regression infrastructure, and best-practice enablement for predictability and quality.
  • Lead physical verification and signoff (DRC/LVS, STA, power/IR/EM, reliability as applicable) and drive tape release readiness with clear signoff criteria.
  • Serve as the primary physical design interface to external CMOS/BiCMOS foundries and partners, ensuring alignment on PDKs, signoff requirements, and tapeout execution.
  • Own project execution across the physical design lifecycle—planning, resourcing, schedules, milestones, and risk mitigation—to deliver predictable tapeouts and product readiness.

Qualifications

Must-have Qualifications

  • B.S. or M.S. in Electrical Engineering or Computer Engineering (or equivalent experience).
  • 7+ years of relevant experience in digital ASIC physical design, including successful tape releases.
  • 5+ years of project/program management experience, including planning, dependency management, risk tracking, and cross-team execution to tapeout.

Preferred Qualifications

  • Demonstrated people leadership, including mentoring and coaching engineers, developing future technical leaders, and building an inclusive, high-accountability culture.
  • Expertise in physical implementation and layout methodology, including timing closure, signoff, and power/performance/area optimization.
  • Working knowledge of DFT methodologies (e.g., scan insertion/test considerations) and how they impact physical design, closure, and tape release.
  • Strong EE fundamentals with experience spanning ASIC design concepts, IP integration, and CMOS/BiCMOS processes.
  • Strong teamwork and problem-solving skills, with clear written and verbal communication across engineering and program stakeholders.
  • Leadership skills to drive change and influence cross-functional teams toward execution goals, quality, and predictable delivery.
  • Sound technical judgment under schedule pressure, with a track record of making effective PPA trade-offs while maintaining signoff quality.

ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight’s ability to obtain any required government authorizations.

We are unable to support visa sponsorship for this position.

MIN $151,000.00 -   MAX $253,000.00

Most offers will be between the minimum and the midpoint of the Salary Range listed above.

#LI-MO1

Note: For other locations, pay ranges will vary by region

US Employees may be eligible for the following benefits:

  • Medical, dental and vision
  • Health Savings Account
  • Health Care and Dependent Care Flexible Spending Accounts
  • Life, Accident, Disability insurance
  • Business Travel Accident and Business Travel Health
  • 401(k) Plan
  • Flexible Time Off, Paid Holidays
  • Paid Family Leave
  • Discounts, Perks
  • Tuition Reimbursement
  • Adoption Assistance
  • ESPP (Employee Stock Purchase Plan)

Careers Privacy Statement***Keysight is an Equal Opportunity Employer.***

Qualifications:

Must-have Qualifications

  • B.S. or M.S. in Electrical Engineering or Computer Engineering (or equivalent experience).
  • 7+ years of relevant experience in digital ASIC physical design, including successful tape releases.
  • 5+ years of project/program management experience, including planning, dependency management, risk tracking, and cross-team execution to tapeout.

Preferred Qualifications

  • Demonstrated people leadership, including mentoring and coaching engineers, developing future technical leaders, and building an inclusive, high-accountability culture.
  • Expertise in physical implementation and layout methodology, including timing closure, signoff, and power/performance/area optimization.
  • Working knowledge of DFT methodologies (e.g., scan insertion/test considerations) and how they impact physical design, closure, and tape release.
  • Strong EE fundamentals with experience spanning ASIC design concepts, IP integration, and CMOS/BiCMOS processes.
  • Strong teamwork and problem-solving skills, with clear written and verbal communication across engineering and program stakeholders.
  • Leadership skills to drive change and influence cross-functional teams toward execution goals, quality, and predictable delivery.
  • Sound technical judgment under schedule pressure, with a track record of making effective PPA trade-offs while maintaining signoff quality.

ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight’s ability to obtain any required government authorizations.

We are unable to support visa sponsorship for this position.

MIN $151,000.00 -   MAX $253,000.00

Most offers will be between the minimum and the midpoint of the Salary Range listed above.

#LI-MO1

Note: For other locations, pay ranges will vary by region

US Employees may be eligible for the following benefits:

  • Medical, dental and vision
  • Health Savings Account
  • Health Care and Dependent Care Flexible Spending Accounts
  • Life, Accident, Disability insurance
  • Business Travel Accident and Business Travel Health
  • 401(k) Plan
  • Flexible Time Off, Paid Holidays
  • Paid Family Leave
  • Discounts, Perks
  • Tuition Reimbursement
  • Adoption Assistance
  • ESPP (Employee Stock Purchase Plan)

Careers Privacy Statement***Keysight is an Equal Opportunity Employer.***

Education:UNAVAILABLEEmployment Type: UNAVAILABLE

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