PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in ...
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in ...
The engineer will need to show proficiency in ICL/PDL, PTAP/STAP, 1687. It is a requirement that ... Direct DFT experience with at least 8 years in the custom chip (ASIC) design business * Hands-on ...
The engineer will need to show proficiency in ICL/PDL, PTAP/STAP, 1687. It is a requirement that ... Direct DFT experience with at least 8 years in the custom chip (ASIC) design business * Hands-on ...
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in ...
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in ...
ASIC DFT Technical Leader- MBIST
$210K - $305K/yr
Bachelors in Electrical engineering with at least 12+years (or Master's with 10+ years) of experience in ASIC DFT. * Prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes.
ASIC DFT Technical Leader- MBIST
$210K - $305K/yr
Bachelors in Electrical engineering with at least 12+years (or Master's with 10+ years) of experience in ASIC DFT. * Prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes.
As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next ... * 5+ years DRAM or ASIC DFT Design or Verification experience. Preferred Qualifications:
As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next ... * 5+ years DRAM or ASIC DFT Design or Verification experience. Preferred Qualifications:
As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next ... * 5+ years DRAM or ASIC DFT Design or Verification experience. Preferred Qualifications:
As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next ... * 5+ years DRAM or ASIC DFT Design or Verification experience. Preferred Qualifications:
Staff HBM Design Architect - DFT
Richardson, TX · On-site
$146 - $297/hr
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field ... or ASIC DFT design or verification Preferred Qualifications * Experience with HBM, DRAM, or ...
Staff HBM Design Architect - DFT
Richardson, TX · On-site
$146 - $297/hr
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field ... or ASIC DFT design or verification Preferred Qualifications * Experience with HBM, DRAM, or ...
DFT Design Engineer
Austin, TX · On-site
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built ...
DFT Design Engineer
Austin, TX · On-site
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built ...
DFT Design Engineer
Austin, TX · On-site
US citizenship Required We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan ...
DFT Design Engineer
Austin, TX · On-site
US citizenship Required We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan ...
DFT Design Engineer
Austin, TX · On-site
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built ...
DFT Design Engineer
Austin, TX · On-site
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built ...
US citizenship Required We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan ...
US citizenship Required We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan ...
ASIC DFT Technical Leader - CDC
Austin, TX · On-site
$186K - $267K/yr
Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality.
ASIC DFT Technical Leader - CDC
Austin, TX · On-site
$186K - $267K/yr
Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality.
New College Grad - Design Engineer, HBM DFT
$90K - $124K/yr
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent * 0-3 years of experience or relevant internship/research experience in ASIC/SoC design, DFT, or ...
New College Grad - Design Engineer, HBM DFT
$90K - $124K/yr
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent * 0-3 years of experience or relevant internship/research experience in ASIC/SoC design, DFT, or ...
Senior DFT Consultant (Tessent) The Design for Test Consultant will be responsible for supporting ... MSEE preferred, ASIC Design for Test experience, interest in applying engineering skills in a ...
Senior DFT Consultant (Tessent) The Design for Test Consultant will be responsible for supporting ... MSEE preferred, ASIC Design for Test experience, interest in applying engineering skills in a ...
Senior DFT Consultant (Tessent) The Design for Test Consultant will be responsible for supporting ... MSEE preferred, ASIC Design for Test experience, interest in applying engineering skills in a ...
Senior DFT Consultant (Tessent) The Design for Test Consultant will be responsible for supporting ... MSEE preferred, ASIC Design for Test experience, interest in applying engineering skills in a ...
Senior Principal DFT Design Engineer
Austin, TX · On-site
$124K - $171K/yr
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built ...
Senior Principal DFT Design Engineer
Austin, TX · On-site
$124K - $171K/yr
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built ...
Senior DFT Consultant (Tessent) The Design for Test Consultant will be responsible for supporting ... MSEE preferred, ASIC Design for Test experience, interest in applying engineering skills in a ...
Senior DFT Consultant (Tessent) The Design for Test Consultant will be responsible for supporting ... MSEE preferred, ASIC Design for Test experience, interest in applying engineering skills in a ...
New College Grad - Design Engineer, HBM DFT
Richardson, TX · On-site
$90K - $124K/yr
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent * 0-3 years of experience or relevant internship/research experience in ASIC/SoC design, DFT, or ...
New College Grad - Design Engineer, HBM DFT
Richardson, TX · On-site
$90K - $124K/yr
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent * 0-3 years of experience or relevant internship/research experience in ASIC/SoC design, DFT, or ...
Senior Principal DFT Design Engineer
Austin, TX · On-site
$124K - $171K/yr
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built ...
Senior Principal DFT Design Engineer
Austin, TX · On-site
$124K - $171K/yr
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built ...
Staff HBM Design Architect - DFT
Richardson, TX · On-site
$146K - $297K/yr
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field ... or ASIC DFT design or verification Preferred Qualifications: * Experience with HBM, DRAM, or ...
Staff HBM Design Architect - DFT
Richardson, TX · On-site
$146K - $297K/yr
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field ... or ASIC DFT design or verification Preferred Qualifications: * Experience with HBM, DRAM, or ...
Asic Dft Engineer information
What is the difference between Asic Dft Engineer vs Asic Verification Engineer?
| Aspect | Asic Dft Engineer | Asic Verification Engineer |
|---|---|---|
| Primary Focus | Design for Testability (DFT) implementation and validation | Functional verification of ASIC designs |
| Skills & Certifications | RTL design, DFT tools, scripting languages | Hardware description languages, verification methodologies |
| Work Environment | Design teams, DFT tool suites | Verification environments, simulation tools |
| Industry Usage | Semiconductor, electronics manufacturing | Semiconductor, electronics design companies |
While both roles are integral to ASIC development, Asic Dft Engineers focus on ensuring designs are testable and manufacturable, whereas Asic Verification Engineers concentrate on verifying the correctness of the design before fabrication.
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For Asic Dft Engineer jobs in Texas, the most frequently searched job titles are:
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Cities in Texas with the most Asic Dft Engineer job openings:
SpaceX rating
8.7
Based on 149 frontline employees who took The Breakroom Quiz
17th of 72 rated aerospace companies
Job description
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
BASIC QUALIFICATIONS:
PREFERRED SKILLS AND EXPERIENCE:
ADDITIONAL REQUIREMENTS:
ITAR REQUIREMENTS:
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
- Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
- Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post-silicon testing and validation support
- Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
- Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
- Run and debug non-timing and SDF annotated gate level simulations
- Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C+
BASIC QUALIFICATIONS:
- Bachelor's degree in electrical engineering, computer engineering or computer science
- 10+ years of experience working with ASICs
- 10+ years of experience in scan insertion and DFT setup, integration and validation
PREFERRED SKILLS AND EXPERIENCE:
- Leadership experience driving SOC DFT execution from concept through tapeout and product deployment
- RTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFT
- Ability to solve complex problems including clock domain crossings and power optimization
- Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience
- Familiar with advanced silicon process and technology nodes for high speed and low power consumption
- Strong implementation or integration of design blocks using Verilog/SystemVerilog
- Experience working with ATE testers and test teams
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours and weekends as needed to meet critical milestones
ITAR REQUIREMENTS:
- Learn more about the ITAR here.
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to
About SpaceX
Sourced by ZipRecruiter
Industry
Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications
Company size
1,001 - 5,000 Employees
Headquarters location
Hawthorne, CA, US