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Asic Development Engineer Jobs in Colorado (NOW HIRING)

IP Integration Engineer

Fort Collins, CO · On-site

$102K - $138K/yr

IP Integration Engineer Broadcom's ASIC Product Division (APD) is focused on enabling customers to ... ASIC products. The successful candidate will be involved in the development of the physical ...

As a Senior ASIC/FPGA Verification Engineer, you will be an integral part of the Avionics development team. You will architect, develop and execute test benches, verify requirements, collect ...

IP Integration Engineer

Fort Collins, CO · On-site

$102K - $138K/yr

IP Integration Engineer Broadcom's ASIC Product Division (APD) is focused on enabling customers to ... ASIC products. The successful candidate will be involved in the development of the physical ...

... development. * Assist in timing analysis, power planning, IR/EM checks, and post-route optimization. * Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.

Design Engineer

Fort Collins, CO · On-site

$60K - $96K/yr

... development. * Assist in timing analysis, power planning, IR/EM checks, and post-route optimization. * Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.

Staff FPGA Design Engineer

Berthoud, CO · On-site

$123K - $169K/yr

S. in Electrical Engineering with 10+ years of direct experience in electronics hardware and ASIC/FPGA development * Demonstrated experience in delivering flight avionics for aircraft, launch ...

New

Staff FPGA Design Engineer

Berthoud, CO · On-site

$123K - $169K/yr

S. in Electrical Engineering with 10+ years of direct experience in electronics hardware and ASIC/FPGA development * Demonstrated experience in delivering flight avionics for aircraft, launch ...

Staff FPGA Design Engineer

Berthoud, CO

$123K - $169K/yr

S. in Electrical Engineering with 10+ years of direct experience in electronics hardware and ASIC/FPGA development * Demonstrated experience in delivering flight avionics for aircraft, launch ...

New

Job #216852 Chipton-Ross is seeking an FPGA Design Engineer for a contract opportunity in Littleton ... Support other aspects of ASIC and FPGA development such as architecture, design, analysis, and test.

... development * Hands-on experience with ASIC/FPGA/system bring-up, system-level debug, and failure ... Master's degree or PhD in Computer Engineering, Electrical Engineering, or a related field * 10+ ...

Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of ... Demonstrate knowledge and development of a test bench with self-checking and simulation (including ...

Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of ... Demonstrate knowledge and development of a test bench with self-checking and simulation (including ...

Senior FPGA Engineer

Englewood, CO · On-site

$130K - $185K/yr

Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of ... Demonstrate knowledge and development of a test bench with self-checking and simulation (including ...

Verification Engineer

Englewood, CO · Hybrid

$130K - $200K/yr

... Engineer to join our VLSI team. What you will be doing * Plan & implement UVM verification ... Proficiency in FPGA/ASIC Verification development methodology * Proficiency in System Verilog and ...

Verification Engineer

Englewood, CO · Hybrid

$130K - $200K/yr

... Engineer to join our VLSI team. What you will be doing * Plan & implement UVM verification ... Proficiency in FPGA/ASIC Verification development methodology * Proficiency in System Verilog and ...

Verification Engineer

Englewood, CO · Hybrid

$130K - $200K/yr

... Engineer to join our VLSI team. What you will be doing * Plan & implement UVM verification ... Proficiency in FPGA/ASIC Verification development methodology * Proficiency in System Verilog and ...

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Asic Development Engineer information

What engineer makes $500,000 a year?

An experienced ASIC Development Engineer working in high-demand sectors such as semiconductor design or advanced chip development can earn $500,000 or more annually, especially with seniority, specialized skills, and in competitive markets. Compensation often includes base salary, bonuses, and stock options, particularly in large tech or semiconductor companies.

What is the difference between Asic Development Engineer vs FPGA Design Engineer?

AspectAsic Development EngineerFPGA Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; knowledge of ASIC design toolsBachelor's or Master's in Electrical Engineering, Digital Design; familiarity with FPGA development tools
Work EnvironmentDesigning and verifying custom silicon chips in semiconductor labs or R&D centersDeveloping and testing FPGA-based solutions in hardware labs or embedded systems environments
Industry UsageUsed in semiconductor companies, integrated circuit design firms, and tech giantsCommon in telecommunications, aerospace, and embedded systems industries

While both roles involve digital hardware design, Asic Development Engineers focus on creating custom chips for high-performance applications, whereas FPGA Design Engineers work on programmable hardware solutions. Both require strong digital design skills and familiarity with hardware description languages, but their end products and development environments differ.

What engineers make $300,000 a year?

Senior engineers in high-demand fields such as software engineering, data engineering, and ASIC development can earn $300,000 or more annually, especially with extensive experience, specialized skills, and working in competitive industries or companies. Roles like senior hardware or ASIC design engineers often reach this level with advanced technical expertise and leadership responsibilities.

Are ASIC engineers in demand?

ASIC development engineers are in high demand due to the growth of industries like consumer electronics, telecommunications, and automotive systems that require custom integrated circuits. Skills in hardware description languages such as VHDL or Verilog, along with experience in FPGA prototyping and verification, enhance employability in this field.

How much do ASIC engineers make?

ASIC development engineers typically earn between $80,000 and $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools can earn higher salaries, often exceeding $150,000.
What are popular job titles related to Asic Development Engineer jobs in Colorado? For Asic Development Engineer jobs in Colorado, the most frequently searched job titles are:
What job categories do people searching Asic Development Engineer jobs in Colorado look for? The top searched job categories for Asic Development Engineer jobs in Colorado are:
What cities in Colorado are hiring for Asic Development Engineer jobs? Cities in Colorado with the most Asic Development Engineer job openings:
Infographic showing various Asic Development Engineer job openings in Colorado as of July 2026, with employment types broken down into 3% Locum Tenens, 82% Full Time, 5% Part Time, 2% Contract, and 8% Summer. Highlights an 88% Physical, 6% Hybrid, and 6% Remote job distribution.
IP Integration Engineer

IP Integration Engineer

Broadcom

Fort Collins, CO • On-site

$102K - $138K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 26 days ago


Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

11th of 142 rated electronics manufacturers


Job description

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Job Description:

IP Integration Engineer

Broadcom's ASIC Product Division (APD) is focused on enabling customers to develop products with a sustainable and substantial competitive advantage. APD does this by delivering best in class technology platforms, easy to integrate bleeding edge intellectual property, and by providing world class customer support. APD's customers span a wide range of industries developing ASICs for largest and most complex cloud computing AI engines, supercomputers, networking, to low power and most advanced wireless solutions, as some examples.

The IP Integration Engineer will be part of a cross functional design team developing die-to-die and die-to-memory PHY IP. The PHYs are used broadly in APD's custom silicon ASIC products. The successful candidate will be involved in the development of the physical composition (hardening of the PHY) as well as developing methodologies for integrating these into large complex 2.5D and 3.5D ASICs. This individual must be highly motivated and capable of working both independently and as part of a team. This position is located in Fort Collins, CO.

Job Requirements:

  • A Bachelor's Degree in Electrical or Computer Engineering and 12+ years of related experience; or Masters degree and 10+ years of related experience

  • Understanding of design trade offs for power, area, and speed in ASIC designs.

  • Have an understanding of the ASIC design flow including FET design, RTL, synthesis, timing, floorplanning, power planning, P&R, LVS, DRC, ...

  • Basic understanding of modern FET architecture including FinFET and Gate All-Around (GAA) topologies.

  • Experience with Cadence Innovus or equivalent toolset

  • Experience in reading timing reports from static timing tools such as Tempus or Primetime.

  • Strong verbal, written communication

  • Team player that can easily work with different personalities and skill levels

  • Ability to multitask and manage multiple technical issues in parallel

  • Well organized, methodical, and detail oriented

  • Must develop, accurately track, and meet commitments to product or engineering development schedules

Desired:

  • Experience with the Cadence Virtuoso design environment

  • Experience or coursework with RTL languages (i.e SystemVerilog, Verilog, VHDL)

  • Experience scripting in Skill, TCL, Ruby, Bash, Perl, Python, etc..

  • Familiar with timing reports and strategies for fixing violations

  • Experience or familiarity with Ansys Redhawk

  • Working knowledge with AI tools such as Chat GPT, Gemini, and/or Cursor

Typical Duties Include:

  • Develop a detailed understanding of Broadcom's die-to-die PHYs.

  • Work with multiple cross functional teams--analog design, digital design, physical composition, DFT, timing, and customers--to build PHYs

  • Work with physical composition teams and interposer design teams

  • Work with analog and physical composition teams to optimize the size and power delivery to high IO density PHYs

  • Work with teams to analyze power integrity (droop, EM, etc...) in various use cases and workloads

  • Develop/write PHY integration documentation for ASIC composition teams

  • Develop list of Checklist task for integration of PHY IP into ASICS

  • Work with IP build teams to complete quality crosschecks to ensure the quality of the PHYs

  • Help support customer and ASIC PHY integration questions


Compensation and Benefits


The annual base salary range for this position is USD 129,400.00 To USD 207,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.


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