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Asic Development Engineer Jobs in Colorado (NOW HIRING)

Broadcom, Inc.

Design Verification Engineer

Broomfield, CO · On-site

$137K - $167K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... ASIC developments. The engineer will be responsible for defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and ...

Broadcom

Design Verification Engineer

Fort Collins, CO · On-site

$134K - $164K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... ASIC developments. The engineer will be responsible for defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and ...

Broadcom Corporation

IP Integration Engineer

Fort Collins, CO · On-site

$102K - $138K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

IP Integration Engineer Broadcom's ASIC Product Division (APD) is focused on enabling customers to ... ASIC products. The successful candidate will be involved in the development of the physical ...

Broadcom

IP Integration Engineer

Fort Collins, CO · On-site

$102K - $138K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

IP Integration Engineer Broadcom's ASIC Product Division (APD) is focused on enabling customers to ... ASIC products. The successful candidate will be involved in the development of the physical ...

Broadcom, Inc.

IP Integration Engineer

Fort Collins, CO · On-site

$102K - $138K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

IP Integration Engineer Broadcom's ASIC Product Division (APD) is focused on enabling customers to ... ASIC products. The successful candidate will be involved in the development of the physical ...

Broadcom

Design Engineer

Fort Collins, CO

$60K - $96K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... development. * Assist in timing analysis, power planning, IR/EM checks, and post-route optimization. * Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.

Broadcom, Inc.

Design Engineer

Fort Collins, CO · On-site

$60K - $96K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... development. * Assist in timing analysis, power planning, IR/EM checks, and post-route optimization. * Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.

Ursa Major

Staff FPGA Design Engineer

Berthoud, CO

$123K - $169K/yr

S. in Electrical Engineering with 10+ years of direct experience in electronics hardware and ASIC/FPGA development * Demonstrated experience in delivering flight avionics for aircraft, launch ...

Ursa Major Technologies

Staff FPGA Design Engineer

Berthoud, CO · On-site

$123K - $169K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

S. in Electrical Engineering with 10+ years of direct experience in electronics hardware and ASIC/FPGA development * Demonstrated experience in delivering flight avionics for aircraft, launch ...

Ursa Major

Staff FPGA Design Engineer

Berthoud, CO · On-site

$123K - $169K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

S. in Electrical Engineering with 10+ years of direct experience in electronics hardware and ASIC/FPGA development * Demonstrated experience in delivering flight avionics for aircraft, launch ...

Industrious Ventures

Staff FPGA Design Engineer

Berthoud, CO · On-site

$150 - $180/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

S. in Electrical Engineering with 10+ years of direct experience in electronics hardware and ASIC/FPGA development. * Demonstrated experience in delivering flight avionics for aircraft, launch ...

InvestedintheMission

Staff FPGA Design Engineer

Berthoud, CO · On-site

$150 - $180/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

S. in Electrical Engineering with 10+ years of direct experience in electronics hardware and ASIC/FPGA development * Demonstrated experience in delivering flight avionics for aircraft, launch ...

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All JobsAsic Development Engineer JobsAsic Development Engineer Jobs in Colorado

Asic Development Engineer information

What is the difference between Asic Development Engineer vs FPGA Design Engineer?

AspectAsic Development EngineerFPGA Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; knowledge of ASIC design toolsBachelor's or Master's in Electrical Engineering, Digital Design; familiarity with FPGA development tools
Work EnvironmentDesigning and verifying custom silicon chips in semiconductor labs or R&D centersDeveloping and testing FPGA-based solutions in hardware labs or embedded systems environments
Industry UsageUsed in semiconductor companies, integrated circuit design firms, and tech giantsCommon in telecommunications, aerospace, and embedded systems industries

While both roles involve digital hardware design, Asic Development Engineers focus on creating custom chips for high-performance applications, whereas FPGA Design Engineers work on programmable hardware solutions. Both require strong digital design skills and familiarity with hardware description languages, but their end products and development environments differ.

Are ASIC Development Engineers in demand?

ASIC Development Engineers are in high demand due to the growing need for custom hardware solutions in industries like telecommunications, consumer electronics, and automotive. Skilled engineers with knowledge of hardware description languages such as VHDL or Verilog, along with experience in FPGA and ASIC design, are particularly sought after in the technology sector.

How much do ASIC development engineers make?

ASIC development engineers typically earn between $80,000 and $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools can earn higher salaries, often exceeding $150,000.

What does an ASIC development engineer do?

An ASIC development engineer designs, develops, and tests application-specific integrated circuits (ASICs) used in electronic devices. They work with hardware description languages like VHDL or Verilog, collaborate with cross-functional teams, and use CAD tools to create efficient chip architectures that meet performance and power specifications.

What are popular job titles related to Asic Development Engineer jobs in Colorado?

For Asic Development Engineer jobs in Colorado, the most frequently searched job titles are:

What job categories do people searching Asic Development Engineer jobs in Colorado look for?

The top searched job categories for Asic Development Engineer jobs in Colorado are:

What cities in Colorado are hiring for Asic Development Engineer jobs?

Cities in Colorado with the most Asic Development Engineer job openings:

Asic Development Engineer jobs near you
Infographic showing various Asic Development Engineer job openings in Colorado as of August 2026, with employment types broken down into 1% As Needed, 82% Full Time, 15% Part Time, and 2% Contract. Highlights an 91% Physical, 3% Hybrid, and 6% Remote job distribution.

Design Verification Engineer

Broadcom, Inc.

Broomfield, CO • On-site

$137K - $167K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 28 days ago

Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

19th of 159 rated electronics manufacturers

Job description

Please Note:
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Job Description:
Design Verification Engineer
Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer that will be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom's ASIC developments.
The engineer will be responsible for defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and debug. This position may involve working with emulation and FPGA prototyping platforms and leading efforts in evaluating and driving the adoption of advanced verification methodologies/flows. The engineer will be expected to develop functional models to facilitate the block, system, and ASIC level verification. The candidate must work closely with the design teams and EDA vendors to accomplish the modeling and verification tasks.
The candidate must have experience using SystemVerilog and UVM, designing verification components including UVM agents, checkers, and behavioral models. Experience with implementing and achieving coverage goals by developing random & directed test cases, and SystemVerilog Assertions. This engineer will be responsible for analyzing and debugging simulation failures at the RTL and gate-level. The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing such formats in the verification context.
Requirements:
  • 12+ years of experience with verification concepts and architectures for complex digital and MXS circuits
  • Experience verifying designs at the block and system levels.
  • Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)
  • Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits
  • Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)
  • Experience with Synopsys, Cadence, and Mentor simulations tools
  • Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments
  • Experience with Perl/Python and Tcl or other scripting languages
  • Experience with version control systems (DesignSync, git)
  • Superior writing, grammar, and verbal communication skills
  • Excellent problem solver; develops and employs automated processes where applicable
  • Worked independently and in a global team and dynamic environment in a highly visible role
  • Possesses ability to learn and adapt to new tools and methodologies on the fly
  • Must have legal authorization to work in the US

It is a plus if the candidate has expertise in one or more of the following areas:
  • Experience with hardware design and debug
  • Experience with emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platforms
  • Formal verification concepts / experience is a plus
  • Experience with verifying iJTAG network using ICL and PDL in the Tessent tool a plus
  • Experience with co-simulation a plus

Education and Experience required:
  • BS in Electrical Engineering / Computer Engineering and 12+ years of related experience; or an MS in Electrical Engineering / Computer Engineering and 10+ years of related experience.

Compensation and Benefits
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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