Experience with the ASIC design process and architecture of large SoCs or GPUs. * Programming and ... Digital Rights Management (DRM) standards * Security threat modelling and penetration testing
Experience with the ASIC design process and architecture of large SoCs or GPUs. * Programming and ... Digital Rights Management (DRM) standards * Security threat modelling and penetration testing
Technical Program Manager
Vancouver, WA · On-site
$130K - $150K/yr
Drive cross-functional execution across ASIC/SoC design, verification, physical design, firmware ... Manage silicon development milestones including specification freeze, RTL release, tape-out ...
Technical Program Manager
Vancouver, WA · On-site
$130K - $150K/yr
Drive cross-functional execution across ASIC/SoC design, verification, physical design, firmware ... Manage silicon development milestones including specification freeze, RTL release, tape-out ...
Chipset Power Engineer
Hillsboro, OR · On-site
$250/hr
... management of active power, idle low power and silicon/system limitsStrong fundamentals in digital ASIC design and power of CMOS circuitsStrong technical documentation skills, along with excellent ...
Chipset Power Engineer
Hillsboro, OR · On-site
$250/hr
... management of active power, idle low power and silicon/system limitsStrong fundamentals in digital ASIC design and power of CMOS circuitsStrong technical documentation skills, along with excellent ...
FPGA/RTL Design Engineer - III (W2 Only)
Hillsboro, OR · On-site
$134K - $184K/yr
... managed services and direct placement services to Global 2000 Corporations. Collabera is ranked ... ASIC and/or SoC design flows and methodology, including CPF/UPF flows Experience with industry ...
FPGA/RTL Design Engineer - III (W2 Only)
Hillsboro, OR · On-site
$134K - $184K/yr
... managed services and direct placement services to Global 2000 Corporations. Collabera is ranked ... ASIC and/or SoC design flows and methodology, including CPF/UPF flows Experience with industry ...
Manage relationships between Lattice and customers by establishing relationships with key ... ASIC design using Verilog or VHDL and simulation/verification tools * Experience withLattice ...
Manage relationships between Lattice and customers by establishing relationships with key ... ASIC design using Verilog or VHDL and simulation/verification tools * Experience withLattice ...
Director, SoC Design Engineering
Hillsboro, OR · On-site
$148K - $180K/yr
... management experience - Expertise in SystemVerilog and UVM/OVM verification methodologies ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Director, SoC Design Engineering
Hillsboro, OR · On-site
$148K - $180K/yr
... management experience - Expertise in SystemVerilog and UVM/OVM verification methodologies ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
FPGA Engineering Manager (MTD, Tualatin, OR)
Tualatin, OR · On-site
$155K - $248K/yr
... ASIC or FPGA design * Minimum of 5 years of experience as an FPGA/ASIC project lead, driving ... Experience as a first level manager of an engineering team. * Experience with FPGA Transceiver ...
FPGA Engineering Manager (MTD, Tualatin, OR)
Tualatin, OR · On-site
$155K - $248K/yr
... ASIC or FPGA design * Minimum of 5 years of experience as an FPGA/ASIC project lead, driving ... Experience as a first level manager of an engineering team. * Experience with FPGA Transceiver ...
Director, Engineering
Hillsboro, OR · On-site
... and ASIC/Foundry products.Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product Engineering, and Technology Development teams.Manage schedule, resource ...
Director, Engineering
Hillsboro, OR · On-site
... and ASIC/Foundry products.Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product Engineering, and Technology Development teams.Manage schedule, resource ...
3rd Party IP Engineering Program Manager
Beaverton, OR · On-site
$125 - $150/hr
3rd Party IP Engineering Program Manager Join Apple's Hardware Technologies organization and be a ... Design or working with Analog and/or Digital IP integration in ASIC/SOC/VLSI Designs or similar ...
3rd Party IP Engineering Program Manager
Beaverton, OR · On-site
$125 - $150/hr
3rd Party IP Engineering Program Manager Join Apple's Hardware Technologies organization and be a ... Design or working with Analog and/or Digital IP integration in ASIC/SOC/VLSI Designs or similar ...
We are the Silicon Co-Design Group (SCG). We identify, own, and drive system-level co-design ideas ... Serve as the multi-functional technical authorityacross architecture, ASIC, board/platform, and ...
We are the Silicon Co-Design Group (SCG). We identify, own, and drive system-level co-design ideas ... Serve as the multi-functional technical authorityacross architecture, ASIC, board/platform, and ...
We are the Silicon Co-Design Group (SCG). We identify, own, and drive system-level co-design ideas ... Serve as the multi-functional technical authority across architecture, ASIC, board/platform, and ...
We are the Silicon Co-Design Group (SCG). We identify, own, and drive system-level co-design ideas ... Serve as the multi-functional technical authority across architecture, ASIC, board/platform, and ...
Neuromorphic Front-End Silicon Lead
Hillsboro, OR · On-site
$220K - $311K/yr
... to manage both the design and verification of our neuromorphic chiplets and IP. This principal ... modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV). 3+ years leading silicon ...
Neuromorphic Front-End Silicon Lead
Hillsboro, OR · On-site
$220K - $311K/yr
... to manage both the design and verification of our neuromorphic chiplets and IP. This principal ... modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV). 3+ years leading silicon ...
Neuromorphic Front-End Silicon Lead
Hillsboro, OR · On-site
$220K - $311K/yr
... to manage both the design and verification of our neuromorphic chiplets and IP. This principal ... and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV). • 3+ years leading ...
Neuromorphic Front-End Silicon Lead
Hillsboro, OR · On-site
$220K - $311K/yr
... to manage both the design and verification of our neuromorphic chiplets and IP. This principal ... and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV). • 3+ years leading ...
Neuromorphic Front-End Silicon Lead
Hillsboro, OR · On-site
$250/hr
... to manage both the design and verification of our neuromorphic chiplets and IP. This principal ... modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV). * 3+ years leading silicon ...
New
Neuromorphic Front-End Silicon Lead
Hillsboro, OR · On-site
$250/hr
... to manage both the design and verification of our neuromorphic chiplets and IP. This principal ... modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV). * 3+ years leading silicon ...
New
... M counselling, Product Engineering, Business Intelligence, Data Management, SOA, BPM, Data ... ADMS and/or their equivalent * 6mths+ industry experience in SOC/ASIC verification * 6mths ...
... M counselling, Product Engineering, Business Intelligence, Data Management, SOA, BPM, Data ... ADMS and/or their equivalent * 6mths+ industry experience in SOC/ASIC verification * 6mths ...
With more than 40 years of experience in design and manufacturing of active implantable medical ... Collaborates cross-functionally with ASIC, external device software, systems engineering and ...
With more than 40 years of experience in design and manufacturing of active implantable medical ... Collaborates cross-functionally with ASIC, external device software, systems engineering and ...
Technical Director PCIe Controller Architect
$189K - $352K/yr
Work closely with logic design, verification and physical design teams to define implementation ... Knowledge of front-end ASIC development flow and best practices * Strong verbal and written ...
Technical Director PCIe Controller Architect
$189K - $352K/yr
Work closely with logic design, verification and physical design teams to define implementation ... Knowledge of front-end ASIC development flow and best practices * Strong verbal and written ...
NVIDIA's robust partner ecosystem enables hyperscalers to build an ASIC hybrid AI infrastructure ... Knowledge of system management protocols such as Redfish and IPMI. Demonstrable experience in ...
NVIDIA's robust partner ecosystem enables hyperscalers to build an ASIC hybrid AI infrastructure ... Knowledge of system management protocols such as Redfish and IPMI. Demonstrable experience in ...
NVIDIA's robust partner ecosystem enables hyperscalers to build an ASIC hybrid AI infrastructure ... Knowledge of device management protocols such as MCTP, PLDM and RDE. * Knowledge of system ...
NVIDIA's robust partner ecosystem enables hyperscalers to build an ASIC hybrid AI infrastructure ... Knowledge of device management protocols such as MCTP, PLDM and RDE. * Knowledge of system ...
Senior Customer Technical Enablement and Debug Engineer
Hillsboro, OR · On-site
$141K - $269K/yr
Partner closely with architecture, design, validation, firmware, and software teams * Drive ... Ability to work under pressure and manage high-priority escalations Qualifications: The Minimum ...
Senior Customer Technical Enablement and Debug Engineer
Hillsboro, OR · On-site
$141K - $269K/yr
Partner closely with architecture, design, validation, firmware, and software teams * Drive ... Ability to work under pressure and manage high-priority escalations Qualifications: The Minimum ...
Asic Design Manager information
See Portland, OR salary details
$44.5K - $59.9K
4% of jobs
$59.9K - $75.3K
8% of jobs
$86.6K is the 25th percentile. Wages below this are outliers.
$75.3K - $90.7K
17% of jobs
The median wage is $105K / yr.
$90.7K - $106.1K
22% of jobs
$106.1K - $121.4K
15% of jobs
$121.4K - $136.8K
6% of jobs
$141.7K is the 75th percentile. Wages above this are outliers.
$136.8K - $152.2K
7% of jobs
$152.2K - $167.6K
7% of jobs
$167.6K - $182.9K
8% of jobs
$182.9K - $198.3K
2% of jobs
$198.3K - $213.7K
2% of jobs
$44.5K
$121.4K
$213.7K
How much do asic design manager jobs pay per year?
What does an ASIC Design Manager do?
What are the key skills and qualifications needed to thrive as an ASIC Design Manager?
What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?
What is the difference between Asic Design Manager vs Asic Design Engineer?
| Aspect | Asic Design Manager | Asic Design Engineer |
|---|---|---|
| Responsibilities | Oversees ASIC design projects, manages teams, and coordinates with stakeholders | Performs ASIC design, coding, simulation, and verification tasks |
| Required Skills | Leadership, project management, ASIC design knowledge | Hardware description languages, circuit design, verification skills |
| Experience | Typically 8+ years in ASIC design, with leadership experience | Usually 2-5 years in ASIC design roles |
| Work Environment | Design teams, project planning, cross-functional collaboration | Design labs, simulation environments, coding and testing |
The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.
What are popular job titles related to Asic Design Manager jobs in Portland, OR?
For Asic Design Manager jobs in Portland, OR, the most frequently searched job titles are:
What job categories do people searching Asic Design Manager jobs in Portland, OR look for?
The top searched job categories for Asic Design Manager jobs in Portland, OR are:
What cities near Portland, OR are hiring for Asic Design Manager jobs?
Cities near Portland, OR with the most Asic Design Manager job openings:

Nvidia rating
9.6
Based on 18 frontline employees who took The Breakroom Quiz
6th of 247 rated software companies
Job description
We are now looking for a Senior Security Architect! NVIDIA is seeking a technical leader interested in a chance to define, craft, and guide implementation of HW Root of Trust architecture for our pioneering SoCs and GPUs. You will be expected to take a strong hands-on role, working with diverse teams across both NVIDIA and external partners to meet HW Root of Trust requirements for our client, automotive, gaming and server platforms.
What you'll be doing:
Collaborate across the company to guide the direction of platform security and develop a long-term roadmap for a flexible HW Root of Trust solution that will be integrated into our products, working with hardware, software, research and marketing teams.
Research, design, and develop architecture solutions meeting internal and external security requirements and standards.
Review architectural, microarchitectural and verification specifications published by internal teams to ensure all IPs align with platform security requirements.
Work with customers, partners to identify and address security issues and threats.
What we need to see:
BS, MS, PhD (or equivalent experience) in Electrical Engineering, Computer Science or Computer Engineering.
8+ years of meaningful relevant work or research experience.
Experience with the ASIC design process and architecture of large SoCs or GPUs.
Programming and debugging fundamentals across languages such as: C/C++, Verilog, ARM assembly and Python/Perl scripting
The ability to work in a dynamic customer focused team and strong communication skills are required.
You have directly worked on several of the following:
System architecture for mobile, automotive, gaming or server platforms
SoC security architecture and security fundamentals including secure boot, measured boot and HW root of trust
ARM or RISCV CPU architectures and related security functionality
Cryptography: algorithms, standards, implementation and application
Security mitigations against physical attacks including fault injection and side channel attacks
Remote attestation mechanisms based on TPM or other solutions
Digital Rights Management (DRM) standards
Security threat modelling and penetration testing
Certification standards and compliance testing
NVIDIA is widely considered to be one of the technology world's most desirable employers. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing - with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Today, we are increasingly known as "the AI computing company". We have some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous architect with a genuine passion for advancing innovative security features into silicon? If so, we want to hear from you.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US