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Asic Design Manager Jobs in Portland, OR (NOW HIRING)

Rambus

PE Logic Design

Hillsboro, OR · Hybrid

$127K - $236K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Rambus

PE Logic Design

Hillsboro, OR · Hybrid

$127K - $236K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Rambus

PE Logic Design

Hillsboro, OR · On-site

$127K - $236K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Rambus.com

PE Logic Design

Hillsboro, OR · On-site

$150 - $200/hr

Solid communication and project management skills * 10+ years of logic design experience(ASIC/FPGA)with BSEE, or * 8+ years of logic designexperience(ASIC/FPGA)with MSEE Definite Plus: * ASIC ...

Rambus

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106K - $198K/yr

Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...

Rambus

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106K - $198K/yr

Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...

Rambus

Hardware Design Engineer

Hillsboro, OR · On-site

$106K - $198K/yr

Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Rambus.com

Principal Logic Design Engineer

Hillsboro, OR · On-site

$150 - $200/hr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus * ASIC ...

Nvidia

Senior ASIC Timing Engineer

Hillsboro, OR · Hybrid

... management. Expertise in analysis and fixing of timing paths through ECOs including crosstalk and ... Experience in physical design and optimization e.g., synthesis, placement, routing, logic ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Nvidia

Senior ASIC Timing Engineer

Hillsboro, OR · Hybrid

... generation and management. * Expertise in analysis and fixing of timing paths through ECOs ... Experience in physical design and optimization e.g., synthesis, placement, routing, logic ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

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Showing results 21-40

All JobsAsic Design JobsAsic Design Manager JobsAsic Design Manager Jobs in Portland, OR

Asic Design Manager information

See Portland, OR salary details

$44.5K

$121.4K

$213.7K

How much do asic design manager jobs pay per year?

As of Sep 8, 2026, the average yearly pay for asic design manager in Portland, OR is $121,418.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,600.00 and $152,700.00 per year, depending on experience, location, and employer.

What does an ASIC Design Manager do?

An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.

What are the key skills and qualifications needed to thrive as an ASIC Design Manager?

To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.

What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?

ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.

What is the difference between Asic Design Manager vs Asic Design Engineer?

AspectAsic Design ManagerAsic Design Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, and coordinates with stakeholdersPerforms ASIC design, coding, simulation, and verification tasks
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification skills
ExperienceTypically 8+ years in ASIC design, with leadership experienceUsually 2-5 years in ASIC design roles
Work EnvironmentDesign teams, project planning, cross-functional collaborationDesign labs, simulation environments, coding and testing

The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.

What are popular job titles related to Asic Design Manager jobs in Portland, OR?

For Asic Design Manager jobs in Portland, OR, the most frequently searched job titles are:

What job categories do people searching Asic Design Manager jobs in Portland, OR look for?

The top searched job categories for Asic Design Manager jobs in Portland, OR are:

What cities near Portland, OR are hiring for Asic Design Manager jobs?

Cities near Portland, OR with the most Asic Design Manager job openings:

Asic Design Manager jobs near you
Infographic showing various Asic Design Manager job openings in Portland, OR as of August 2026, with employment types broken down into 86% Full Time, 12% Part Time, and 2% Contract. Highlights an 84% Physical, 2% Hybrid, and 14% Remote job distribution, with an average salary of $121,418 per year, or $58.4 per hour.

PE Logic Design

Rambus

Hillsboro, OR • Hybrid

$127K - $236K/yr

Full-time

Medical, Dental, Retirement

Posted 19 days ago

Job description

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic Design Engineer to join our Silicon IP (SIP) team in Hillsboro, Oregon. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. 

In this role, the candidate will be reporting to the Director of Engineering as an individual contributor. As a Principal Logic Design Engineer, you will play a pivotal role in the micro-architecture and design of our next- generation high performance and cutting-edge memory controllers for data centers and AI applications. This is a fast-growing market with high demand from tier-1 customers which gives ample opportunity for innovation and differentiation. If you like challenges and want to make a technical difference in the memory landscape during these exciting times in the semiconductor industry, this is the right opportunity for you. 

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. 


  • Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces 
  • Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitative data 
  • Collaborate closely with verification team to shape test plans and improve verification coverage 
  • Work with physical design team to understand and resolve timing, power, and congestion challenges 
  • Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary 
  • Provide technical support to FAE team on pre-sales customer engagements 
  • Provide technical support to AE team on post-sales customer deliveries 

  • Strong System Verilog/Verilog RTL design expertise 
  • Questa/Incisive/VCS simulator experience 
  • Python/Perl/TCL scripting experience 
  • Ability to learn quickly and work independently 
  • Solid communication and project management skills 
  • 10+ years of logic design experience (ASIC/FPGA) with BSEE, or  
  • 8+ years of logic design experience (ASIC/FPGA) with MSEE 

Definite Plus: 

  • ASIC synthesis, timing constraint, CDC/RDC experience 
  • UVM Verification experience 
  • Memory (HBM, LPDDR) expertise 
  • AMBA AXI or CHI design experience 

About Rambus 

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.  

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.  

The US salary range for this full-time position is $127,400 to $236,600

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