Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...
Field Application Engineer - Tessent Design for Test (DFT)
Wilsonville, OR · On-site
$100 - $130/hr
Proven track record of Design for Test for ASIC design * Demonstrated knowledge of TCL language and programming concepts * Command of Microsoft Office products * Ideal candidate has experience with ...
Field Application Engineer - Tessent Design for Test (DFT)
Wilsonville, OR · On-site
$100 - $130/hr
Proven track record of Design for Test for ASIC design * Demonstrated knowledge of TCL language and programming concepts * Command of Microsoft Office products * Ideal candidate has experience with ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...
NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This ... As a senior member of our verification team, you'll understand the design & implementation with ...
NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This ... As a senior member of our verification team, you'll understand the design & implementation with ...
ASIC Physical Design Principal Consultant
$148K - $152K/yr
At least 10 years of experience in VLSI/ASIC Design. * At least 9 years of experience in Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing ...
ASIC Physical Design Principal Consultant
$148K - $152K/yr
At least 10 years of experience in VLSI/ASIC Design. * At least 9 years of experience in Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
... mixed signal ASIC and FPGA designs. Document design work, present results, and participate in ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
... mixed signal ASIC and FPGA designs. Document design work, present results, and participate in ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
Senior Engineer, Digital Design Engineering
$121K - $174K/yr
... mixed signal ASIC and FPGA designs. Document design work, present results, and participate in ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
Senior Engineer, Digital Design Engineering
$121K - $174K/yr
... mixed signal ASIC and FPGA designs. Document design work, present results, and participate in ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
Master's Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent ... Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design ...
Master's Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent ... Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design ...
Principal Logic Design Engineer Position Description: Protingent Staffing has an exciting Direct ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * AMBA AXI or ...
Principal Logic Design Engineer Position Description: Protingent Staffing has an exciting Direct ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * AMBA AXI or ...
Semiconductor Design Engineer (Compute Test, Oregon)
Tualatin, OR · On-site
$155 - $248/hr
Experience with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred ... Job Segment Testing, Design Engineer, Manufacturing Engineer, Test Engineer, Business Process ...
Semiconductor Design Engineer (Compute Test, Oregon)
Tualatin, OR · On-site
$155 - $248/hr
Experience with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred ... Job Segment Testing, Design Engineer, Manufacturing Engineer, Test Engineer, Business Process ...
We are now looking for a Senior Logic Design Engineer. As a member of our CPU Logic Design Team ... Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ...
We are now looking for a Senior Logic Design Engineer. As a member of our CPU Logic Design Team ... Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ...
Verilog expertise is preferredas is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO. * Strong communication and interpersonal skills are required along ...
Verilog expertise is preferredas is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO. * Strong communication and interpersonal skills are required along ...
SoC Logic Design Engineer
$141K - $200K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in advancing Intel ... Hands-on experience from spec to timing closure in at least one SoC/ASIC design We encourage you to ...
SoC Logic Design Engineer
$141K - $200K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in advancing Intel ... Hands-on experience from spec to timing closure in at least one SoC/ASIC design We encourage you to ...
Semiconductor Design Engineer (Compute Test, Oregon)
Tualatin, OR · On-site
$154K - $247K/yr
Opportunity Overview The Semiconductor Design Engineer will play a key role within Teradyne ... Experience with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred.
Semiconductor Design Engineer (Compute Test, Oregon)
Tualatin, OR · On-site
$154K - $247K/yr
Opportunity Overview The Semiconductor Design Engineer will play a key role within Teradyne ... Experience with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred.
Semiconductor Design Engineer (Compute Test, Oregon)
Tualatin, OR · On-site
$154K - $247K/yr
Opportunity Overview The Semiconductor Design Engineer will play a key role within Teradyne ... Experience with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred.
Semiconductor Design Engineer (Compute Test, Oregon)
Tualatin, OR · On-site
$154K - $247K/yr
Opportunity Overview The Semiconductor Design Engineer will play a key role within Teradyne ... Experience with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred.
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $287K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $287K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $287K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $287K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Asic Design Engineer information
See Portland, OR salary details
$99.7K - $110.1K
16% of jobs
$110.1K - $120.5K
3% of jobs
$120.5K - $130.9K
4% of jobs
$134K is the 25th percentile. Wages below this are outliers.
$130.9K - $141.3K
6% of jobs
The median wage is $147.9K / yr.
$141.3K - $151.7K
33% of jobs
$151.7K - $162.2K
3% of jobs
$162.2K - $172.6K
2% of jobs
$179.4K is the 75th percentile. Wages above this are outliers.
$172.6K - $183K
12% of jobs
$183K - $193.4K
5% of jobs
$193.4K - $203.8K
4% of jobs
$203.8K - $214.2K
12% of jobs
$99.7K
$159.3K
$214.2K
How much do asic design engineer jobs pay per year?
As of Sep 2, 2026, the average yearly pay for asic design engineer in Portland, OR is $159,283.00, according to ZipRecruiter salary data. Most workers in this role earn between $139,500.00 and $190,900.00 per year, depending on experience, location, and employer.
What is an ASIC design engineer?
ASIC Design Engineers are professionals who design and develop Application-Specific Integrated Circuits (ASICs), which are custom-built semiconductor chips tailored for specific applications or products. They are responsible for the entire design process, including architecture definition, logic design, verification, synthesis, and sometimes physical layout. Their work is crucial in industries like consumer electronics, telecommunications, automotive, and more, ensuring that devices have optimized performance, power efficiency, and functionality for their intended uses.
What does an ASIC design engineer do?
An application specific integrated circuit (ASIC) is an electronic circuit created for a specific purpose, rather than for general use. ASIC design engineers create product design specification (PDS) statements for ASIC, optimize logic design, and create architectural design models. ASIC design engineers often work on a team to deliver ASIC design solutions for standard and complex computing. Knowledge of computer-aided design (CAD) tools, logic simulation, Verilog, and other hardware description languages (HDLs) is integral to career success.
What are the key skills and qualifications needed to thrive as an ASIC design engineer, and why are they important?
To thrive as an ASIC Design Engineer, you need a solid background in electrical engineering, digital logic design, and proficiency with hardware description languages like Verilog or VHDL, usually backed by a relevant degree. Familiarity with EDA tools such as Synopsys or Cadence and knowledge of simulation and verification methodologies are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork set outstanding engineers apart in this role. These skills and qualities are vital for delivering complex, high-performance integrated circuits that meet strict specifications and project deadlines.
What are some common challenges faced by ASIC design engineers during the design and verification phases?
ASIC Design Engineers often encounter challenges such as meeting strict performance and power constraints while ensuring that the design remains within budget and time limits. Debugging complex logic errors during simulation and verification can be particularly demanding, as small mistakes can have significant downstream effects. Additionally, effective communication with cross-functional teams—including software, hardware, and validation engineers—is essential to resolve integration issues and meet project milestones. Adapting to rapidly evolving tools and technologies is also a key part of the role.
What is the difference between Asic Design Engineer vs FPGA Design Engineer?
| Aspect | Asic Design Engineer | FPGA Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Designing custom chips for manufacturing | Developing programmable logic designs for prototyping and deployment |
| Industry Usage | Semiconductor companies, consumer electronics, automotive | Prototyping, testing, and specialized hardware applications |
Both roles require similar educational backgrounds and often overlap in skills like HDL programming. However, Asic Design Engineers focus on creating chips for mass production, while FPGA Design Engineers work on flexible, reprogrammable hardware for testing and specific applications.
Are ASIC design engineers in demand?
ASIC design engineers are in high demand due to the growth of semiconductor technology, consumer electronics, and data centers. Skills in hardware description languages like VHDL or Verilog, along with experience in FPGA and ASIC development, increase employability in this field.
How much does an ASIC design engineer make?
The average salary for an ASIC design engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools can earn higher salaries, often exceeding $180,000.
More about Asic Design Engineer jobs
What are the most commonly searched types of Asic Design Engineer jobs in Portland, OR?
The most popular types of Asic Design Engineer jobs in Portland, OR are:
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For Asic Design Engineer jobs in Portland, OR, the most frequently searched job titles are:
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Cities near Portland, OR with the most Asic Design Engineer job openings:
Apple rating
8.1
Based on 680 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that encourages the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something - you’ll add something.
Description
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Preferred Qualifications
This position requires detailed knowledge of the ASIC design timing closure flow and methodology.
The ideal candidate will have at least 2+ years of experience in writing ASIC timing constraints and timing closure, expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues, hands on experience in timing/SDC constraints generation and management, proficient in scripting languages (Tcl and Perl), Familiarity with synthesis, DFT and backend related methodology and tools.
Strong communication skills are a pre-requisite. You will be collaborating with many diverse groups at Apple.
The ideal candidate will be a self starter and highly motivated to be successful at Apple.
Minimum Qualifications
BS degree in technical discipline with minimum 10 years of proven experience.
Description
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Preferred Qualifications
This position requires detailed knowledge of the ASIC design timing closure flow and methodology.
The ideal candidate will have at least 2+ years of experience in writing ASIC timing constraints and timing closure, expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues, hands on experience in timing/SDC constraints generation and management, proficient in scripting languages (Tcl and Perl), Familiarity with synthesis, DFT and backend related methodology and tools.
Strong communication skills are a pre-requisite. You will be collaborating with many diverse groups at Apple.
The ideal candidate will be a self starter and highly motivated to be successful at Apple.
Minimum Qualifications
BS degree in technical discipline with minimum 10 years of proven experience.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976