We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ...
SoC Logic Design Engineer
Hillsboro, OR · On-site
$141K - $200K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in advancing Intel ... Hands-on experience from spec to timing closure in at least one SoC/ASIC design We encourage you to ...
SoC Logic Design Engineer
Hillsboro, OR · On-site
$141K - $200K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in advancing Intel ... Hands-on experience from spec to timing closure in at least one SoC/ASIC design We encourage you to ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
In this role, you will be working with some of the brightest inventors and engineers in the world ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127.40 - $236.60/hr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127.40 - $236.60/hr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Collaborate with ASIC design and architecture teams to align on automation approaches. * Adapt modern software engineering workflows to GPU architecture development and find opportunities to set a ...
Collaborate with ASIC design and architecture teams to align on automation approaches. * Adapt modern software engineering workflows to GPU architecture development and find opportunities to set a ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ... Experience providing technical direction to engineering teams and customer support * Customer ...
Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ... Experience providing technical direction to engineering teams and customer support * Customer ...
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Knowledge of the CMOS ASIC design flow. Job Type:Experienced Hire Shift:Shift 1 (United States of ...
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Knowledge of the CMOS ASIC design flow. Job Type:Experienced Hire Shift:Shift 1 (United States of ...
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Knowledge of the CMOS ASIC design flow. Job Type: Experienced Hire Shift: Shift 1 (United States of ...
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Knowledge of the CMOS ASIC design flow. Job Type: Experienced Hire Shift: Shift 1 (United States of ...
SoC Logic Design Engineer
Hillsboro, OR · On-site
$141K - $232K/yr
The Role and Impact Join Intel's distinguished team as an SoC Logic Design Engineer. In this role ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
SoC Logic Design Engineer
Hillsboro, OR · On-site
$141K - $232K/yr
The Role and Impact Join Intel's distinguished team as an SoC Logic Design Engineer. In this role ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
SoC Logic Design Engineer
$141K - $232K/yr
The Role and Impact Join Intel's distinguished team as an SoC Logic Design Engineer. In this role ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
SoC Logic Design Engineer
$141K - $232K/yr
The Role and Impact Join Intel's distinguished team as an SoC Logic Design Engineer. In this role ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Integrated Circuit Design Verification Engineer
Vancouver, WA · On-site
$142K - $173K/yr
We're looking for a Integrated Circuit Design Verification Engineer to join the Spectacles Team at ... Familiarity with ASIC test or production flow * Ideal candidate is a self-starter, can organise ...
Integrated Circuit Design Verification Engineer
Vancouver, WA · On-site
$142K - $173K/yr
We're looking for a Integrated Circuit Design Verification Engineer to join the Spectacles Team at ... Familiarity with ASIC test or production flow * Ideal candidate is a self-starter, can organise ...
Integrated Circuit Design Verification Engineer
$142K - $173K/yr
We're looking for a Integrated Circuit Design Verification Engineer to join the Spectacles Team at ... Familiarity with ASIC test or production flow * Ideal candidate is a self-starter, can organise ...
Integrated Circuit Design Verification Engineer
$142K - $173K/yr
We're looking for a Integrated Circuit Design Verification Engineer to join the Spectacles Team at ... Familiarity with ASIC test or production flow * Ideal candidate is a self-starter, can organise ...
Asic Design Engineer information
See Portland, OR salary details
$99.7K - $110.1K
16% of jobs
$110.1K - $120.5K
3% of jobs
$120.5K - $130.9K
4% of jobs
$134K is the 25th percentile. Wages below this are outliers.
$130.9K - $141.3K
6% of jobs
The median wage is $147.9K / yr.
$141.3K - $151.7K
33% of jobs
$151.7K - $162.2K
3% of jobs
$162.2K - $172.6K
2% of jobs
$179.4K is the 75th percentile. Wages above this are outliers.
$172.6K - $183K
12% of jobs
$183K - $193.4K
5% of jobs
$193.4K - $203.8K
4% of jobs
$203.8K - $214.2K
12% of jobs
$99.7K
$159.3K
$214.2K
How much do asic design engineer jobs pay per year?
As of Aug 8, 2026, the average yearly pay for asic design engineer in Portland, OR is $159,283.00, according to ZipRecruiter salary data. Most workers in this role earn between $139,500.00 and $190,900.00 per year, depending on experience, location, and employer.
What is the difference between Asic Design Engineer vs FPGA Design Engineer?
| Aspect | Asic Design Engineer | FPGA Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Designing custom chips for manufacturing | Developing programmable logic designs for prototyping and deployment |
| Industry Usage | Semiconductor companies, consumer electronics, automotive | Prototyping, testing, and specialized hardware applications |
Both roles require similar educational backgrounds and often overlap in skills like HDL programming. However, Asic Design Engineers focus on creating chips for mass production, while FPGA Design Engineers work on flexible, reprogrammable hardware for testing and specific applications.
How much does an ASIC design engineer make?
An ASIC design engineer's salary typically ranges from $80,000 to $150,000 annually, depending on experience, location, and industry. Senior engineers with specialized skills in hardware description languages and verification tools can earn higher compensation, often exceeding $180,000.
What are some common challenges faced by ASIC design engineers during the design and verification phases?
ASIC Design Engineers often encounter challenges such as meeting strict performance and power constraints while ensuring that the design remains within budget and time limits. Debugging complex logic errors during simulation and verification can be particularly demanding, as small mistakes can have significant downstream effects. Additionally, effective communication with cross-functional teams—including software, hardware, and validation engineers—is essential to resolve integration issues and meet project milestones. Adapting to rapidly evolving tools and technologies is also a key part of the role.
Are ASIC design engineers in demand?
ASIC design engineers are in high demand due to the growth of semiconductor technology, consumer electronics, and data centers. Skills in hardware description languages like VHDL or Verilog, along with experience in FPGA and ASIC development, are highly valued in the industry.
What are the key skills and qualifications needed to thrive as an ASIC design engineer, and why are they important?
To thrive as an ASIC Design Engineer, you need a solid background in electrical engineering, digital logic design, and proficiency with hardware description languages like Verilog or VHDL, usually backed by a relevant degree. Familiarity with EDA tools such as Synopsys or Cadence and knowledge of simulation and verification methodologies are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork set outstanding engineers apart in this role. These skills and qualities are vital for delivering complex, high-performance integrated circuits that meet strict specifications and project deadlines.
What is an ASIC design engineer?
ASIC Design Engineers are professionals who design and develop Application-Specific Integrated Circuits (ASICs), which are custom-built semiconductor chips tailored for specific applications or products. They are responsible for the entire design process, including architecture definition, logic design, verification, synthesis, and sometimes physical layout. Their work is crucial in industries like consumer electronics, telecommunications, automotive, and more, ensuring that devices have optimized performance, power efficiency, and functionality for their intended uses.
What does an ASIC design engineer do?
An application specific integrated circuit (ASIC) is an electronic circuit created for a specific purpose, rather than for general use. ASIC design engineers create product design specification (PDS) statements for ASIC, optimize logic design, and create architectural design models. ASIC design engineers often work on a team to deliver ASIC design solutions for standard and complex computing. Knowledge of computer-aided design (CAD) tools, logic simulation, Verilog, and other hardware description languages (HDLs) is integral to career success.
More about Asic Design Engineer jobs
What are the most commonly searched types of Asic Design Engineer jobs in Portland, OR? The most popular types of Asic Design Engineer jobs in Portland, OR are:
What are popular job titles related to Asic Design Engineer jobs in Portland, OR? For Asic Design Engineer jobs in Portland, OR, the most frequently searched job titles are:
What job categories do people searching Asic Design Engineer jobs in Portland, OR look for? The top searched job categories for Asic Design Engineer jobs in Portland, OR are:
What cities near Portland, OR are hiring for Asic Design Engineer jobs? Cities near Portland, OR with the most Asic Design Engineer job openings:
Full-time
Re-posted 23 days ago
Nvidia rating
9.6
Based on 17 frontline employees who took The Breakroom Quiz
8th of 242 rated software companies
Job description
We are now looking for a Senior Logic Design Engineer!
As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence! We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
What you'll be doing:
As a member of our core CPU team, you'll own and be responsible for crafting and timely delivery of a specific unit on the chip.
Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation.
Collaborate with our verification team to verify the correctness of your unit.
Work with implementation to achieve your timing, area, performance and power goals.
Assist with timing closure of super units.
What we need to see:
Master's Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
5+ years of experience in processor or other related high performance semiconductor designs.
Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
Strong communication and interpersonal skills are required along with the work in a dynamic, global team. Your successful track record of mentoring junior engineers and interns a huge plus.
A strong background in computer architecture, cache coherency or high speed interconnects is helpful
NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most brilliant and hardworking people in the world working for us. Are you creative and autonomous and love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993