We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has ... flows to improve our chip yield and to address multiple sectors, defines Reset and Boot ...
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has ... flows to improve our chip yield and to address multiple sectors, defines Reset and Boot ...
ASIC Design Leader
Crane, IN · On-site
Oversee data collection exercises and acceptance testing of on-chip technologies. * Develop use ... Lead design, integration, and testing efforts through both hands-on and delegated approaches.
ASIC Design Leader
Crane, IN · On-site
Oversee data collection exercises and acceptance testing of on-chip technologies. * Develop use ... Lead design, integration, and testing efforts through both hands-on and delegated approaches.
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team. NVIDIA has ... flows to improve our chip yield and to address multiple sectors, defines Reset and Boot ...
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team. NVIDIA has ... flows to improve our chip yield and to address multiple sectors, defines Reset and Boot ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Hands on experience in all aspects of front‑end chip development process (e.g., CDC/RDC, LINT ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Hands on experience in all aspects of front‑end chip development process (e.g., CDC/RDC, LINT ...
Lead feasibility studies and transistor-level design of mixed-signal building blocks including ADCs ... OR Master's degree in Science, Engineering, or related field and 7+ years of ASIC design ...
Lead feasibility studies and transistor-level design of mixed-signal building blocks including ADCs ... OR Master's degree in Science, Engineering, or related field and 7+ years of ASIC design ...
... ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or ... senior designer role * Expert-level proficiency in SystemVerilog RTL design and coding best ...
... ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or ... senior designer role * Expert-level proficiency in SystemVerilog RTL design and coding best ...
Senior Manager, ASIC Design Engineering
Austin, TX · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL ...
Senior Manager, ASIC Design Engineering
Austin, TX · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL ...
You will lead a team designing SoC ASICs and the intellectual property functions going into them ... chip architecture decisions and micro-architecture trade-offs - Recruit, hire, and retain top ...
You will lead a team designing SoC ASICs and the intellectual property functions going into them ... chip architecture decisions and micro-architecture trade-offs - Recruit, hire, and retain top ...
... SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Contribute towards pre‑silicon verification, chip bring‑up and post‑silicon validation * Be a ...
... SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Contribute towards pre‑silicon verification, chip bring‑up and post‑silicon validation * Be a ...
... SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Contribute towards pre-silicon verification, chip bring-up and post-silicon validation * Be a hands ...
... SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Contribute towards pre-silicon verification, chip bring-up and post-silicon validation * Be a hands ...
Senior Manager, ASIC Design Engineering
San Jose, CA · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL ...
Senior Manager, ASIC Design Engineering
San Jose, CA · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL ...
Sr. ASIC Design Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Contribute towards pre-silicon verification, chip bring-up and post-silicon validation * Be a hands ...
Sr. ASIC Design Verification Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Contribute towards pre-silicon verification, chip bring-up and post-silicon validation * Be a hands ...
Sr. ASIC Design Verification Engineer (Silicon Engineering)
Redmond, WA · On-site
$165K - $260K/yr
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Contribute towards pre-silicon verification, chip bring-up and post-silicon validation * Be a hands ...
Sr. ASIC Design Verification Engineer (Silicon Engineering)
Redmond, WA · On-site
$165K - $260K/yr
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Contribute towards pre-silicon verification, chip bring-up and post-silicon validation * Be a hands ...
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Contribute towards pre-silicon verification, chip bring-up and post-silicon validation * Be a hands ...
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Contribute towards pre-silicon verification, chip bring-up and post-silicon validation * Be a hands ...
Apply LLMs, coding agents, and agentic systems - to core ASIC design problems: RTL generation ... Push the limits of what's possible in chip design with models and research harnesses on top of open ...
Apply LLMs, coding agents, and agentic systems - to core ASIC design problems: RTL generation ... Push the limits of what's possible in chip design with models and research harnesses on top of open ...
You will lead a team designing SoC ASICs and the intellectual property functions going into them ... chip architecture decisions and micro-architecture trade-offs - Recruit, hire, and retain top ...
You will lead a team designing SoC ASICs and the intellectual property functions going into them ... chip architecture decisions and micro-architecture trade-offs - Recruit, hire, and retain top ...
ASIC Design and Integration Engineer
Beaverton, OR · On-site
$184K - $324K/yr
Familiarity with custom ASIC design and FPGA prototyping ... Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC ...
ASIC Design and Integration Engineer
Beaverton, OR · On-site
$184K - $324K/yr
Familiarity with custom ASIC design and FPGA prototyping ... Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC ...
Apply LLMs, coding agents, and agentic systems - to core ASIC design problems: RTL generation ... Deliver against NVIDIA's internal chip design schedules and activities - your success is measured ...
Apply LLMs, coding agents, and agentic systems - to core ASIC design problems: RTL generation ... Deliver against NVIDIA's internal chip design schedules and activities - your success is measured ...
ASIC Design and Integration Engineer
Beaverton, OR · On-site
$150K - $277K/yr
Familiarity with custom ASIC design and FPGA prototyping ... Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC ...
ASIC Design and Integration Engineer
Beaverton, OR · On-site
$150K - $277K/yr
Familiarity with custom ASIC design and FPGA prototyping ... Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC ...
Apply LLMs, coding agents, and agentic systems - to core ASIC design problems: RTL generation ... Deliver against NVIDIA's internal chip design schedules and activities - your success is measured ...
Apply LLMs, coding agents, and agentic systems - to core ASIC design problems: RTL generation ... Deliver against NVIDIA's internal chip design schedules and activities - your success is measured ...
Asic Design Chip Lead information
See salary details
$39.66 - $43.53
18% of jobs
$46.24 is the 25th percentile. Wages below this are outliers.
$43.53 - $47.40
10% of jobs
$47.40 - $51.27
7% of jobs
$51.27 - $55.14
5% of jobs
$55.14 - $59
6% of jobs
The median wage is $60.94 / hr.
$59 - $62.87
6% of jobs
$62.87 - $66.74
13% of jobs
$66.74 - $70.61
1% of jobs
$71.90 is the 75th percentile. Wages above this are outliers.
$70.61 - $74.48
25% of jobs
$74.48 - $78.34
4% of jobs
$78.34 - $82.21
4% of jobs
$39
$60
$82
How much do asic design chip lead jobs pay per hour?
What does an ASIC Design Chip Lead do?
How does an ASIC Design Chip Lead typically collaborate with cross-functional teams during a project lifecycle?
What are the key skills and qualifications needed to thrive as an ASIC Design Chip Lead, and why are they important?
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For Asic Design Chip Lead jobs, the most frequently searched job titles are:

Senior ASIC Design Engineer
Santa Clara, CA • Hybrid
Full-time
Re-posted 29 days ago
Nvidia rating
9.6
Based on 18 frontline employees who took The Breakroom Quiz
Job description
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can tackle, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. Make the choice to join us today.
NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading GPU and SoC's. With the System-ASIC team, you will contribute to designing multiple products that will be used in a variety of applications from consumer graphics to self-driving cars and the growing field of artificial intelligence. System-ASIC team works closely with System Architecture team on product definitions, implements new innovative flows to improve our chip yield and to address multiple sectors, defines Reset and Boot Architecture and implements them in complex GPU and Tegra chips. The team is also handling the architecture, design, and synthesis of multiple System-level modules.
What you'll be doing:
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs
Collaborate with architects, ASIC designers, and verification engineers to design sophisticated system-level modules such as Floorsweep, In-silicon measurement, Reset and Boot controllers.
You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules.
Integrate modules into the overall SOC design and work closely with other teams in the silicon bring-up process and ensure successful SOC level integration.
You will also use your expertise to identify and implement improvements in the current design flow and methodologies to improve efficiency and quality.
What we need to see:
BS / MS in Microelectronics/ Electronic Engineering/ Computer Science and related (or equivalent experience).
5+ years of ASIC design experience or SOC integration design / flow experience
Fundamental digital design concepts and experience in ASIC design flow including RTL design, verification, logic synthesis and timing analysis
Strong coding skills in Perl, Python, C++, or other industry-standard scripting languages
Basic understanding of verification methodology
Excellent analytical and problem-solving skills and attention to detail.
Ways to stand out from the crowd:
Familiarity with ARM CPU and SoC system architecture, microprocessor, and microcontroller fundamentals (caches, buses, memory controllers, DMA, etc.)
Experience with reset controllers, boot, fuse controllers or UCIe protocol
Hands-on experience in programming (C/C++) and scripting (Perl/Python).
# LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US