You're an experienced ASIC/FPGA design engineer who has delivered meaningful work and is now asking ... Lead chip design initiatives from architectural concept through production release. * Provide ...
You're an experienced ASIC/FPGA design engineer who has delivered meaningful work and is now asking ... Lead chip design initiatives from architectural concept through production release. * Provide ...
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Contribute towards pre-silicon verification, chip bring-up and post-silicon validation * Be a hands ...
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... Contribute towards pre-silicon verification, chip bring-up and post-silicon validation * Be a hands ...
You're an experienced ASIC/FPGA design engineer who has delivered meaningful work and is now asking ... Lead chip design initiatives from architectural concept through production release. * Provide ...
You're an experienced ASIC/FPGA design engineer who has delivered meaningful work and is now asking ... Lead chip design initiatives from architectural concept through production release. * Provide ...
ASIC Design-for-Test (DFT)
San Jose, CA · On-site
Role: Lead ASIC DFT Engineer Location: San Jose, CA Work Setup: Remote, PST time zone Nbr of ... DFT Architecture definition. - Must Full chip / Sub system level DFT activities - Must Scan ...
Quick apply
ASIC Design-for-Test (DFT)
San Jose, CA · On-site
Role: Lead ASIC DFT Engineer Location: San Jose, CA Work Setup: Remote, PST time zone Nbr of ... DFT Architecture definition. - Must Full chip / Sub system level DFT activities - Must Scan ...
Senior ASIC Chip Lead / Project Lead (TERADYNE, Agoura Hills, CA)
Agoura Hills, CA · On-site
$192K - $307K/yr
Coordinate outsourced design partners, EDA vendors, IP suppliers, and foundry partners. * Resolve technical and program conflicts while balancing quality, cost, and schedule objectives. * Drive ...
Senior ASIC Chip Lead / Project Lead (TERADYNE, Agoura Hills, CA)
Agoura Hills, CA · On-site
$192K - $307K/yr
Coordinate outsourced design partners, EDA vendors, IP suppliers, and foundry partners. * Resolve technical and program conflicts while balancing quality, cost, and schedule objectives. * Drive ...
Senior Chip Lead Engineer-SoC/ASIC
San Jose, CA · On-site
$143K/yr
You're an experienced ASIC/FPGA design engineer who has delivered meaningful work and is now asking ... Lead chip design initiatives from architectural concept through production release. * Provide ...
Senior Chip Lead Engineer-SoC/ASIC
San Jose, CA · On-site
$143K/yr
You're an experienced ASIC/FPGA design engineer who has delivered meaningful work and is now asking ... Lead chip design initiatives from architectural concept through production release. * Provide ...
Senior ASIC Design Engineer
Beaverton, OR · On-site
Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Collaborate with other team members to integrate the block with the full chip * Use Verilog to ...
Senior ASIC Design Engineer
Beaverton, OR · On-site
Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Collaborate with other team members to integrate the block with the full chip * Use Verilog to ...
SoC (system on chip), Security, ASIC, Digital Design, Crypto, Cryptography, Encryption, side-channel, subsystem, lead Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related ...
SoC (system on chip), Security, ASIC, Digital Design, Crypto, Cryptography, Encryption, side-channel, subsystem, lead Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related ...
Senior ASIC Chip Lead / Project Lead (TERADYNE, Agoura Hills, CA)
Agoura Hills, CA · On-site
$192K - $307K/yr
Coordinate outsourced design partners, EDA vendors, IP suppliers, and foundry partners. * Resolve technical and program conflicts while balancing quality, cost, and schedule objectives. * Drive ...
Senior ASIC Chip Lead / Project Lead (TERADYNE, Agoura Hills, CA)
Agoura Hills, CA · On-site
$192K - $307K/yr
Coordinate outsourced design partners, EDA vendors, IP suppliers, and foundry partners. * Resolve technical and program conflicts while balancing quality, cost, and schedule objectives. * Drive ...
ASIC Design Engineer
Santa Clara, CA · On-site
$126K - $190K/yr
This role is hands-on and requires ownership of the design through the complete ASIC lifecycle ... Chip interconnect (NOC) implementation Qualcomm is an equal opportunity employer. If you are an ...
ASIC Design Engineer
Santa Clara, CA · On-site
$126K - $190K/yr
This role is hands-on and requires ownership of the design through the complete ASIC lifecycle ... Chip interconnect (NOC) implementation Qualcomm is an equal opportunity employer. If you are an ...
Chip Lead
Austin, TX · Hybrid
$101K - $133K/yr
AI & Chip Engineering team defines and develops System on Chip, ASIC's, Digital and Analog IP'sfor ... Overall, Chip lead is central design point of contact for all cross functional teams associated ...
Chip Lead
Austin, TX · Hybrid
$101K - $133K/yr
AI & Chip Engineering team defines and develops System on Chip, ASIC's, Digital and Analog IP'sfor ... Overall, Chip lead is central design point of contact for all cross functional teams associated ...
Chip Lead
Austin, TX · On-site
$101K - $133K/yr
AI & Chip Engineering team defines and develops System on Chip, ASIC's, Digital and Analog IP's for ... Overall, Chip lead is central design point of contact for all cross functional teams associated ...
Chip Lead
Austin, TX · On-site
$101K - $133K/yr
AI & Chip Engineering team defines and develops System on Chip, ASIC's, Digital and Analog IP's for ... Overall, Chip lead is central design point of contact for all cross functional teams associated ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC ...
Senior Analog/Mixed Signal ASIC Design Engineer
Cambridge, MA · On-site
$82K - $205K/yr
We are involved in the full design lifecycle and often take chip-lead roles on our projects. We're ... experience with a PhD in ASIC Hardware Engineering or related. Additional Additional ...
Senior Analog/Mixed Signal ASIC Design Engineer
Cambridge, MA · On-site
$82K - $205K/yr
We are involved in the full design lifecycle and often take chip-lead roles on our projects. We're ... experience with a PhD in ASIC Hardware Engineering or related. Additional Additional ...
Cornelis Networks is looking for a Senior ASIC Design Engineering Manager to lead and grow our RTL ... full-chip milestones. Success requires deep hands-on expertise in advanced RTL design ...
Cornelis Networks is looking for a Senior ASIC Design Engineering Manager to lead and grow our RTL ... full-chip milestones. Success requires deep hands-on expertise in advanced RTL design ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC ...
Senior Analog/Mixed Signal ASIC Design Engineer with Security Clearance
Cambridge, MA · On-site
$82K - $205K/yr
We are involved in the full design lifecycle and often take chip-lead roles on our projects. We're ... experience with a PhD in ASIC Hardware Engineering or related. Additional Additional ...
Senior Analog/Mixed Signal ASIC Design Engineer with Security Clearance
Cambridge, MA · On-site
$82K - $205K/yr
We are involved in the full design lifecycle and often take chip-lead roles on our projects. We're ... experience with a PhD in ASIC Hardware Engineering or related. Additional Additional ...
Senior Analog/Mixed Signal ASIC Design Engineer
Cambridge, MA · On-site
$82K - $205K/yr
We are involved in the full design lifecycle and often take chip-lead roles on our projects. We're ... experience with a PhD in ASIC Hardware Engineering or related. Additional Additional ...
Senior Analog/Mixed Signal ASIC Design Engineer
Cambridge, MA · On-site
$82K - $205K/yr
We are involved in the full design lifecycle and often take chip-lead roles on our projects. We're ... experience with a PhD in ASIC Hardware Engineering or related. Additional Additional ...
Senior ASIC Design Engineer
OR · On-site +1
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team. NVIDIA has ... flows to improve our chip yield and to address multiple sectors, defines Reset and Boot ...
Senior ASIC Design Engineer
OR · On-site +1
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team. NVIDIA has ... flows to improve our chip yield and to address multiple sectors, defines Reset and Boot ...
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has ... flows to improve our chip yield and to address multiple sectors, defines Reset and Boot ...
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has ... flows to improve our chip yield and to address multiple sectors, defines Reset and Boot ...
Asic Design Chip Lead information
See salary details
$39.66 - $43.53
18% of jobs
$46.24 is the 25th percentile. Wages below this are outliers.
$43.53 - $47.40
10% of jobs
$47.40 - $51.27
7% of jobs
$51.27 - $55.14
5% of jobs
$55.14 - $59
6% of jobs
The median wage is $60.94 / hr.
$59 - $62.87
6% of jobs
$62.87 - $66.74
13% of jobs
$66.74 - $70.61
1% of jobs
$71.90 is the 75th percentile. Wages above this are outliers.
$70.61 - $74.48
25% of jobs
$74.48 - $78.34
4% of jobs
$78.34 - $82.21
4% of jobs
$39
$60
$82
How much do asic design chip lead jobs pay per hour?
What does an ASIC Design Chip Lead do?
How does an ASIC Design Chip Lead typically collaborate with cross-functional teams during a project lifecycle?
What are the key skills and qualifications needed to thrive as an ASIC Design Chip Lead, and why are they important?
What are popular job titles related to Asic Design Chip Lead jobs?
For Asic Design Chip Lead jobs, the most frequently searched job titles are:

Senior Chip Lead Engineer-SoC/ASIC
San Jose, CA • On-site
Other
Posted 5 days ago
Advanced Micro Devices rating
8.6
Based on 13 frontline employees who took The Breakroom Quiz
28th of 162 rated electronics manufacturers
Job description
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.
Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.
THE ROLEWe're seeking a T-shaped engineer ready to elevate their impact.
You're an experienced ASIC/FPGA design engineer who has delivered meaningful work and is now asking, "What's next?" You're ready to broaden your scope, deepen your influence, and tackle challenges that span the entire chip development spectrum, from architecture through production shipment.
This is not a traditional engineering role. You won't be confined to a single discipline or siloed within one functional area. Instead, you'll serve as a technical partner to chip leads across dynamic, cross-functional teams, bringing both breadth and depth to solve complex technical challenges.
You'll build the strategic perspective, cross-functional fluency, and leadership presence needed to own full chip programs while making significant technical contributions from day one. If you're energized by variety, collaboration, and the opportunity to shape silicon from concept through production, we'd love to talk.
THE PERSONYou are a technically versatile engineer with deep expertise in one or more semiconductor domains and a broad understanding of the complete chip development lifecycle.
You thrive in ambiguous environments, approach challenges with curiosity and a growth mindset, and continuously seek opportunities to expand your technical and leadership capabilities. You are self-directed, proactive, and collaborative, with the ability to influence teams and drive alignment without relying on formal authority.
You excel at balancing technical depth with program-level perspective and enjoy working across organizational boundaries to deliver successful products.
KEY RESPONSIBILITIES Technical Leadership- Lead chip design initiatives from architectural concept through production release.
- Provide technical guidance across all phases of the chip development lifecycle, engaging domain experts when appropriate.
- Drive technical decisions in ambiguous and rapidly evolving project environments.
- Develop a broad understanding of system-level tradeoffs while maintaining expertise in key technical areas.
- Partner with chip leads and program managers to support scheduling, resource planning, and risk mitigation.
- Interface with customers, foundries, IP vendors, and EDA tool suppliers.
- Coordinate activities across hardware, software, systems, validation, and product teams.
- Build alignment and drive consensus among diverse stakeholders.
- Navigated complex situations with limited direction and establish clear execution plans.
- Identify and resolve complex technical challenges throughout the design flow.
- Apply analytical thinking and creative problem-solving approaches to overcome obstacles.
- Drive continuous improvement in design methodologies, development processes, and engineering practices.
- Contribute to technical strategy and long-term organizational capability growth.
- 10+ years of semiconductor industry experience.
- 8+ years of hands‑on ASIC and/or FPGA design experience.
- Demonstrated experience across multiple phases of chip development including:
- Architecture definition and specification
- RTL development
- Verification and validation
- Physical design
- Package development
- Power optimization
- Silicon validation and characterization
- Manufacturing and production ramp
- System software development including device drivers and low-level software
- Experience working in ambiguous environments and adapting to changing requirements.
- Deep technical expertise in one or more semiconductor disciplines combined with a broad understanding of the full chip development lifecycle.
- Strong knowledge of:
- SoC and subsystem architecture
- RTL design and synthesis
- Verification methodologies
- Physical design principles
- Timing closure
- Power optimization techniques
- Manufacturing test and DFT methodologies
- Silicon bring-up and debug
- Package development and production ramp processes
- Knowledge of ASIC and FPGA design tools and methodologies.
- Proficiency with Verilog, VHDL, and/or SystemVerilog.
- Working knowledge of industry‑ standard EDA tools.
- Understanding of semiconductor manufacturing processes.
- Strong written and verbal communication skills.
- Ability to influence stakeholders and drive outcomes without formal authority.
- Proven collaboration across engineering, business, and organizational boundaries.
- Strong strategic thinking, prioritization, and problem‑solving abilities.
- Self‑directed with a demonstrated growth mindset and learning agility.
- Experience with advanced process nodes (7nm and below).
- Exposure to multiple chip architectures including CPU, GPU, FPGA, AI/ML accelerators, and networking devices.
- Background spanning both ASIC and FPGA development.
- Experience interacting directly with customers, vendors, foundries, and external partners.
- Prior technical leadership, mentoring, team leadership, or management experience.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
- Master's degree preferred.
This role is not eligible for visa sponsorship.
#LI-RL1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
What Advanced Micro Devices employees say
Pay
Benefits
Hours and flexibility
Workplace
Get the full story on Breakroom
About Advanced Micro Devices (AMD)
Sourced by ZipRecruiter
Industry
Computer and electronic product manufacturing and manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Sunnyvale, CA, US