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Analog Physical Verification Engineer Jobs (NOW HIRING)

Intel

Physical Verification Engineer

Hillsboro, OR

$148K/yr

Position Overview The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout ...

Analog Devices

Principal EDA Engineer

Wilmington, MA · On-site

Learn more at www.analog.com and on LinkedIn and X. ADI is seeking a Principal EDA Engineer with deep expertise in Calibre-based physical verification, code development, and tapeout support for ...

Intel

Physical Verification Engineer

Phoenix, AZ

$135K/yr

Position Overview The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout ...

Intel

Physical Verification Engineer

Santa Clara, CA

$159K/yr

Position Overview The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout ...

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Analog Physical Verification Engineer information

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$186.2K

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How much do analog physical verification engineer jobs pay per year?

As of Sep 14, 2026, the average yearly pay for analog physical verification engineer in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.

What is an analog physical verification engineer?

Analog Physical Verification Engineers are professionals who ensure that analog integrated circuit (IC) designs comply with manufacturing and design specifications. They use specialized software tools to check for layout versus schematic (LVS) mismatches, design rule violations (DRC), and electrical rule checks (ERC) to guarantee the manufacturability and reliability of analog circuits. Their work is essential in the semiconductor industry to prevent costly design errors before silicon fabrication. Typically, they collaborate closely with layout, design, and fabrication teams throughout the IC design cycle.

What are the key skills and qualifications needed to thrive as an analog physical verification engineer?

To thrive as an Analog Physical Verification Engineer, you need a solid background in electrical engineering, semiconductor physics, and experience with analog/mixed-signal circuit design and layout. Familiarity with industry-standard EDA tools like Cadence Virtuoso, Mentor Calibre, and knowledge of DRC/LVS verification flows is essential. Attention to detail, problem-solving abilities, and strong communication skills help ensure accuracy and effective collaboration with design teams. These skills are crucial for delivering robust, manufacturable analog ICs that meet rigorous industry standards.

What are some common challenges faced by analog physical verification engineers during tape-out, and how can they be addressed?

Analog Physical Verification Engineers often encounter challenges such as resolving complex design rule violations, managing parasitic effects, and ensuring layout-versus-schematic (LVS) and design rule check (DRC) closure within tight deadlines during tape-out. These challenges can be addressed by closely collaborating with layout, design, and circuit teams, leveraging advanced verification tools, and maintaining clear documentation of exceptions and waivers. Proactive communication and early engagement in the design process also help minimize last-minute issues and facilitate a smoother tape-out process.

What is the difference between Analog Physical Verification Engineer vs Digital Physical Verification Engineer?

AspectAnalog Physical Verification EngineerDigital Physical Verification Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI Design, or related fields; knowledge of analog circuit designBachelor's or Master's in Electrical Engineering, VLSI Design, or related fields; familiarity with digital logic design
Work EnvironmentSemiconductor companies, chip design houses, focusing on analog/RF circuitsSemiconductor companies, chip design houses, focusing on digital logic and chip architecture
Industry UsageUsed in analog/RF IC design verification processesUsed in digital IC design verification processes

The main difference between an Analog Physical Verification Engineer and a Digital Physical Verification Engineer lies in their focus areas. Analog verification engineers specialize in verifying analog and RF circuits, requiring expertise in analog design principles. Digital verification engineers focus on digital logic and architecture. Both roles require similar educational backgrounds and work in semiconductor environments, but their technical focus and verification methods differ significantly.

What are popular job titles related to Analog Physical Verification Engineer jobs?

For Analog Physical Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Analog Physical Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 78% Full Time, 17% Part Time, 3% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $186,238 per year, or $89.5 per hour.

Principal Physical Verification Engineer

Irvine, CA • On-site

Celero Communications, Inc.
See more jobs at Celero Communications, Inc.external

$150K - $250K/yr

Other

Posted 26 days ago

Job description

Principal Physical Verification Engineer

  • Irvine, CA


Principal Full-Chip Physical Verification Engineer
Key Responsibilities
Team & Project Leadership

  • Lead full chip Physical Verification effort

  • Own execution plans, schedules for full-chip

  • Drive accountability for quality, milestones, and tapeout readiness.

  • Conduct full chip and blocks PV checks


Physical Verification Ownership

  • Ownership of full chip verification

  • Work with internal analog team to ensure clean IP delivery

  • Responsible for running and analyzing DRC/ERC/LUP/PERC results

  • Experience with using either ICV or Calibre verification tools

  • Understanding advance TSMC DRC rules


Cross-Functional Collaboration

  • Partner with analog, block, chip top owners to ensure clean floorplan

  • Provide early guidance on corner case requirements

  • Influence floorplan constraints, hierarchy, and implementation strategy

  • Participate in tapeout readiness reviews


Required Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering or related field.

  • 7+ years of experience with full-chip verifications


Proven hands-on experience with:

  • Physical Verification tool (ICV/Calibre)

  • Able to assemble a flow to support block/chip level PV


Strong expertise in:

  • Floorplanning to avoid DRC/LVS issues

  • Provide guidance to analog IP team to allow for clean integration


Preferred Qualifications

  • Experience in advanced technology nodes (7nm, 5nm, 3nm)

  • Automation skills using Tcl, Python, or shell scripting


Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)


Javier Leon
Talent Acquisition
619-227-3193 cell/text
javier.leon@celero.inc
www.celero.inc

#J-18808-Ljbffr

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