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Analog Layout Engineer Salary Jobs (NOW HIRING)

Microsoft

Senior Quantum Analog Layout Engineer

Redmond, WA · On-site

$123K - $165K/yr

As a Senior Quantum Analog Layout Engineer on the Quantum 1st Party Hardware ASIC team, you will play a critical leadership role in advancing Microsoft's quantum analog infrastructure, driving Analog ...

Apple, Inc.

Analog Layout Automation Engineer

San Diego, CA · On-site

$214K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Intel

Analog Layout Design Engineer

Austin, TX · On-site

$200K/yr

The Role and Impact Intel is seeking a passionate and skilled Analog Layout Design Engineer to join ... Annual Salary Range for jobs which could be performed in the US: $122,440.00-172,860.00 USD The ...

Intel

Analog Layout Design Engineer

Hillsboro, OR

$220K/yr

The Role and Impact Intel is seeking a passionate and skilled Analog Layout Design Engineer to join ... Annual Salary Range for jobs which could be performed in the US: $122,440.00-172,860.00 USD The ...

Apple

Analog Layout Automation Engineer

San Diego, CA · On-site

$214K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Nokia

Staff Custom Analog Layout Engineer

San Jose, CA · On-site

$139K - $258K/yr

Decent understanding in analog layout requirements, such as matching and shielding; * Has extensive ... Disclaimer for US/Canada Nokia Maintains broad annual base salary ranges for its roles in order to ...

Apple

Analog Layout Automation Engineer

Cupertino, CA · On-site

$249K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Apple

Analog Layout Automation Engineer

San Diego, CA · On-site

$214K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Apple, Inc.

Analog Layout Automation Engineer

Cupertino, CA · On-site

$249K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

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All JobsAnalog Layout Engineer Salary Jobs

Analog Layout Engineer Salary information

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$77K

$186.2K

$203K

How much do analog layout engineer salary jobs pay per year?

As of Aug 15, 2026, the average yearly pay for analog layout engineer salary in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.

Is an analog layout engineer a good career?

An analog layout engineer is a specialized role in integrated circuit design, focusing on creating physical layouts for analog components using tools like Cadence or Synopsys. It offers steady demand in the semiconductor industry, competitive salaries, and opportunities for skill development in circuit design and fabrication processes.

What is the difference between Analog Layout Engineer Salary vs Digital IC Layout Engineer Salary?

AspectAnalog Layout Engineer SalaryDigital IC Layout Engineer Salary
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI DesignBachelor's or Master's in Electrical Engineering, VLSI Design
Work EnvironmentSemiconductor companies, chip design firmsSemiconductor companies, chip design firms
Industry UsageAnalog circuit design, mixed-signal ICsDigital circuit design, digital ICs
Salary Range$80,000 - $130,000$75,000 - $125,000

Both Analog Layout Engineers and Digital IC Layout Engineers typically hold similar educational credentials and work in semiconductor environments. However, Analog Layout Engineers often focus on analog and mixed-signal ICs, which can influence salary differences. Overall, salaries are comparable, with slight variations depending on experience and location.

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Analog Layout Engineer Salary jobs near you
Infographic showing various Analog Layout Engineer Salary job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 10% Part Time, and 2% Contract. Highlights an 91% Physical, 3% Hybrid, and 6% Remote job distribution, with an average salary of $186,238 per year, or $89.5 per hour.

Senior Quantum Analog Layout Engineer

Microsoft

Redmond, WA • On-site

$123K - $165K/yr

Full-time

Re-posted 5 days ago

Microsoft rating

8.5

Company rating: 8.5 out of 10

Based on 132 frontline employees who took The Breakroom Quiz

79th of 244 rated software companies

Job description

Overview
Microsoft's Quantum team is building the first scalable, fault-tolerant quantum computer, advancing everything from quantum hardware and error correction to Azure integration. Our full-stack strategy spans the physics of quantum devices through scalable readout and control infrastructures powered by cryo-electronics. As quantum computing enters a pivotal phase of accelerated growth, this position offers a unique opportunity to contribute meaningfully to a transformative technology, such as the Application Specific Integrated Circuits (ASICs) and analog circuitry developed by this team.
As a Senior Quantum Analog Layout Engineer on the Quantum 1st Party Hardware ASIC team, you will play a critical leadership role in advancing Microsoft's quantum analog infrastructure, driving Analog Layout designs and coordinating employees, contingent staff, and external vendors to deliver high-quality designs.
Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities
  • Deliver Schematic-to-Graphic Database System (GDS) layouts for cutting-edge, high-performance, high-speed, low-power IP designs, including interconnectivity solutions and foundational Analog circuit blocks. Execute these layouts across multiple process nodes, including deep Fin Field-Effect Transistor (FinFET), following industry best practices.
  • Develop plans for Analog Mask Layout execution and follow processes and methodologies to deliver IP blocks. Coordinate tasks with junior layout team members as needed.
  • Using Cadence Virtuoso (or other equivalent) design tools and flows; perform layout implementation of analog-intensive IPs and help establish flows, methodologies, and processes for execution alongside peers.
  • Support the on-boarding and off-boarding of contingent layout staff and vendor partners as needed; help direct their day-to-day execution to ensure quality and schedule are met.
  • Work with other members of the team to deliver IPs, including project planning, schedule tracking, and report generation. Follow, augment, or put in place processes and methodologies for high-quality execution alongside peers.
  • Other
    • Embody our culture and values.

Qualifications
Required/minimum qualifications
  • Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position
    • OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment
    • OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
    • OR equivalent experience.

Other Requirements
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
    • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
    • Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. § 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
  • Ability to leverage AI tools to drive innovation and efficiency (e.g., performance modeling and analysis, research gathering, day to day task automation).
  • Ability to work in an "AI-first" environment using modern AI tools to accelerate discovery through hardware development.

Preferred Qualifications
  • 10+ years of experience in Analog Mask Layout execution and IP delivery, including delivery of medium-to-large complexity analog blocks into mass production.
  • 5+ years of lead experience covering day-to-day task coordination and overall delivery responsibilities across a layout team.
  • Proficient use of Electronic Design Automation (EDA) tools from Cadence, Mentor, and Synopsys, including advanced Schematic-Driven Layout (SDL).
  • Hands-on layout experience with high-performance analog blocks such as Voltage-Controlled Oscillators (VCOs), charge pumps, interpolators, bandgap references, Operational Transconductance Amplifiers (OTAs), Phase-Locked Loops (PLLs), Analog-to-Digital and Digital-to-Analog Converters (ADCs/DACs), Low-Dropout Regulators (LDOs), Serializer/Deserializers (SerDes), and other foundational analog blocks.
  • In-depth knowledge of analog design and layout guidelines for high-performance, high-speed, and/or low-power designs, including floor-planning, block-level routing, and large macro-level assemblies.
  • Knowledge of industry-standard analog layout techniques such as common-centroid layout, matching, symmetrical layouts, signal shielding, use of dummy devices, and thermal-aware layouts with consideration for Electromigration/IR-drop (EM/IR) and other analog-specific guidelines.
  • Demonstrated ability to coordinate execution with external vendors and contingent staff, including scoping deliverables, tracking progress, and accepting completed work.
  • Ability to learn cryogenic Process Design Kits (PDKs) and apply analog layout techniques to designs that operate at cryogenic temperatures.

#Quantum #QuantumCareers #MDQCareers
Quantum Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

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About Microsoft

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Our infrastructure is comprised of a large global portfolio of more than 100 datacenters and 1 million servers. Our foundation is built upon and managed by a team of subject matter experts working to support services for more than 1 billion customers and 20 million businesses in over 90 countries worldwide. With environmental sustainability and optimization at the forefront of our datacenter design and operations, we continue to grow and evolve as we meet the ever-changing business demands that hold Microsoft as a world-class cloud provider.

Industry

Computer and computer peripheral equipment and software wholesalers

Company size

10,000+ Employees

Headquarters location

Redmond, WA, US

Year founded

1975

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