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Ai Chip Design Rtl Jobs in Phoenix, AZ (NOW HIRING)

Renesas Electronics

Senior Digital Engineer

Chandler, AZ · On-site

$133K/yr

... RTL for digital CMOS circuit design. * Strong understanding of ASIC design methodology. * Strong understanding of Lint, CDC & RDC tools. * Strong understanding of block-level & chip-level ...

Cirrus Logic

Digital Design Engineer

Chandler, AZ · On-site

$133K/yr

In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...

Renesas Electronics

Senior Digital Engineer

Chandler, AZ · On-site +1

$133K/yr

... RTL for digital CMOS circuit design. * Strong understanding of ASIC design methodology. * Strong understanding of Lint, CDC & RDC tools. * Strong understanding of block-level & chip-level ...

Renesas Electronics

Senior Digital Engineer

Chandler, AZ · On-site +1

$133K/yr

... RTL for digital CMOS circuit design. * Strong understanding of ASIC design methodology. * Strong understanding of Lint, CDC & RDC tools. * Strong understanding of block-level & chip-level ...

Cirrus Logic

Staff Digital Design Engineer

Chandler, AZ · On-site

$133K/yr

In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...

Cirrus Logic

Senior Digital Design Engineer

Chandler, AZ · On-site

$133K/yr

In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...

Intel

Director, Engineering

Phoenix, AZ

Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product ... Experience driving AI-enabled design productivity and design automation initiatives.Proven track ...

Intel

Memory Circuit Design Engineer

Phoenix, AZ

Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si ... leadership for the AI era, enabling our customers to design leadership products, global ...

Viasat, Inc.

Hardware Design Engineer

Tempe, AZ · On-site

$164K - $246K/yr

Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Familiarity with Git, CI/CD practices, and AI development tools (Claude Code, Copilot). Salary ...

Viasat, Inc.

Hardware Design Engineer

Tempe, AZ

$164K - $246K/yr

Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Familiarity with Git, CI/CD practices, and AI development tools (Claude Code, Copilot). Salary ...

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How much do ai chip design rtl jobs pay per year?

As of Sep 3, 2026, the average yearly pay for ai chip design rtl in Phoenix, AZ is $138,380.00, according to ZipRecruiter salary data. Most workers in this role earn between $135,000.00 and $135,000.00 per year, depending on experience, location, and employer.

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What are popular job titles related to Ai Chip Design Rtl jobs in Phoenix, AZ?

For Ai Chip Design Rtl jobs in Phoenix, AZ, the most frequently searched job titles are:

What job categories do people searching Ai Chip Design Rtl jobs in Phoenix, AZ look for?

The top searched job categories for Ai Chip Design Rtl jobs in Phoenix, AZ are:

Ai Chip Design Rtl jobs near you

Principal Engineer, Digital Design Engineer (AI/ML)

Analog Devices

Chandler, AZ • On-site

Full-time

Re-posted 21 days ago

Analog Devices rating

8.7

Company rating: 8.7 out of 10

Based on 19 frontline employees who took The Breakroom Quiz

18th of 161 rated electronics manufacturers

Job description

About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.
As a Principal Digital Design Engineer, you will lead the architecture and implementation of complex digital subsystems within ADI's mixed-signal and power management ICs. You will drive the adoption of AI/ML techniques to transform design automation, optimization, and productivity across the digital design flow. Your work will span multiple business units and directly shape how ADI integrates advanced digital functionality into next-generation products.
Key Responsibilities
  • Drive adoption of AI/ML methodologies to optimize synthesis, timing closure, power estimation, and design space exploration
  • Define and lead digital architecture for complex SoCs and mixed-signal ICs, including control logic, digital interfaces, and on-chip processing
  • Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power targets
  • Own the synthesis-to-signoff flow including synthesis with timing and placement constraints (Genus), STA and power analysis (Tempus), and logical equivalence checking (Conformal)
  • Lead architecture and design reviews, assessing trade-offs across timing, area, power, and testability
  • Influence design flows, IP reuse strategies, and product roadmaps across multiple projects
  • Collaborate with analog design teams to define and integrate digital-analog interfaces and control architectures
Required Skills and Experience
  • MSEE or MSCE with 10+ years of digital IC design experience, or PhD with 8+ years (BSEE/BSCE with equivalent depth considered)
  • Expert-level RTL design in Verilog/SystemVerilog with proven track record of complex digital subsystem delivery
  • Track record of leading digital designs from architecture through tape-out, silicon validation, and production release
  • Strong scripting skills (Python, Tcl, shell) with experience applying AI/ML techniques to enhance productivity
  • Deep knowledge of synthesis, static timing analysis, DFT (scan, ATPG, BIST), and clock domain crossing methodologies
  • Proficiency with Cadence digital design tools: Genus, Innovus, Tempus, Conformal
  • Excellent presentation, technical writing, and communication skills
Preferred Qualifications
  • Working knowledge of place-and-route (Innovus), floorplanning, and physical-aware design techniques
  • Experience with low-power design techniques including multi-voltage domains, power gating, and UPF
  • Familiarity with digital interfaces (I2C, SPI, UART) and mixed-signal SoC integration
  • Strong analytical and problem-solving abilities
  • Ability to work effectively in a collaborative team environment
Technical Scope
  • Development and deployment of AI/ML-driven workflows that measurably improve design quality, turnaround time, or coverage
  • Full digital subsystem architecture ownership from specification through silicon bring-up and production validation
  • Clock domain crossing analysis, lint, and formal verification for multi-clock digital architectures
  • DFT strategy and implementation including scan insertion, ATPG pattern generation, and fault coverage closure
Collaboration and Impact
  • Partner with analog design, verification, and applications teams to define digital control architectures that meet system-level requirements
  • Champion AI/ML-driven improvements to digital design workflows, sharing results and best practices across teams
  • Contribute to organizational knowledge through design reviews and cross-team technical forums

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: No
Shift Type: 1st Shift/Days

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About Analog Devices

Sourced by ZipRecruiter

Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.

Industry

Electrical equipment, appliance, and component manufacturing

Company size

5,001 - 10,000 Employees

Headquarters location

Norwood, MA, US

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