Expertise in CMOS semiconductor device physics and test chip design for advanced transistor device ... leadership for the AI era, enabling our customers to design leadership products, global ...
Expertise in CMOS semiconductor device physics and test chip design for advanced transistor device ... leadership for the AI era, enabling our customers to design leadership products, global ...
Senior Technical Staff Engineer - Verification
Chandler, AZ · On-site
$133K - $163K/yr
Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and ... Continuously improve verification methodologies by leveraging AI/ML automation to reduce the cycle ...
Senior Technical Staff Engineer - Verification
Chandler, AZ · On-site
$133K - $163K/yr
Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and ... Continuously improve verification methodologies by leveraging AI/ML automation to reduce the cycle ...
Senior Technical Staff Engineer - Verification
Chandler, AZ · On-site
$133K - $163K/yr
Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and ... Continuously improve verification methodologies by leveraging AI/ML automation to reduce the cycle ...
Senior Technical Staff Engineer - Verification
Chandler, AZ · On-site
$133K - $163K/yr
Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and ... Continuously improve verification methodologies by leveraging AI/ML automation to reduce the cycle ...
Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
Senior Digital Engineer
Chandler, AZ · On-site
$133K/yr
... RTL for digital CMOS circuit design. * Strong understanding of ASIC design methodology. * Strong understanding of Lint, CDC & RDC tools. * Strong understanding of block-level & chip-level ...
Senior Digital Engineer
Chandler, AZ · On-site
$133K/yr
... RTL for digital CMOS circuit design. * Strong understanding of ASIC design methodology. * Strong understanding of Lint, CDC & RDC tools. * Strong understanding of block-level & chip-level ...
Senior Digital Engineer
Chandler, AZ · On-site +1
$133K/yr
... RTL for digital CMOS circuit design. * Strong understanding of ASIC design methodology. * Strong understanding of Lint, CDC & RDC tools. * Strong understanding of block-level & chip-level ...
Senior Digital Engineer
Chandler, AZ · On-site +1
$133K/yr
... RTL for digital CMOS circuit design. * Strong understanding of ASIC design methodology. * Strong understanding of Lint, CDC & RDC tools. * Strong understanding of block-level & chip-level ...
Senior Digital Engineer
Chandler, AZ · On-site +1
$133K/yr
... RTL for digital CMOS circuit design. * Strong understanding of ASIC design methodology. * Strong understanding of Lint, CDC & RDC tools. * Strong understanding of block-level & chip-level ...
Quick apply
Senior Digital Engineer
Chandler, AZ · On-site +1
$133K/yr
... RTL for digital CMOS circuit design. * Strong understanding of ASIC design methodology. * Strong understanding of Lint, CDC & RDC tools. * Strong understanding of block-level & chip-level ...
Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
Senior Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
Senior Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
... chip designs. This position is at the forefront of innovation, requiring collaboration with cross ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
... chip designs. This position is at the forefront of innovation, requiring collaboration with cross ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
Senior Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
Senior Staff Digital Design Engineer
Chandler, AZ · On-site
$133K/yr
In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
... chip designs. This position is at the forefront of innovation, requiring collaboration with cross ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
... chip designs. This position is at the forefront of innovation, requiring collaboration with cross ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...
Sr. CPU RTL Front End Methodology Engineer
$121K - $167K/yr
... design the next generation of high-performance microprocessors. We are looking for a skilled individual who has hands-on experience in RTL methodologies, coding, debug and effective use of AI tools ...
Sr. CPU RTL Front End Methodology Engineer
$121K - $167K/yr
... design the next generation of high-performance microprocessors. We are looking for a skilled individual who has hands-on experience in RTL methodologies, coding, debug and effective use of AI tools ...
Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product ... Experience driving AI-enabled design productivity and design automation initiatives.Proven track ...
Posted today
Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product ... Experience driving AI-enabled design productivity and design automation initiatives.Proven track ...
Posted today
Senior Engineer I- Design
Chandler, AZ · On-site
... RTL design, functional verification, and contributing to next-generation mixed-signal and digital products. The ideal candidate combines strong hardware design fundamentals with modern AI/ML-assisted ...
Senior Engineer I- Design
Chandler, AZ · On-site
... RTL design, functional verification, and contributing to next-generation mixed-signal and digital products. The ideal candidate combines strong hardware design fundamentals with modern AI/ML-assisted ...
Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si ... leadership for the AI era, enabling our customers to design leadership products, global ...
Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si ... leadership for the AI era, enabling our customers to design leadership products, global ...
Senior Engineer I- Design
Chandler, AZ · On-site
... RTL design, functional verification, and contributing to next-generation mixed-signal and digital products. The ideal candidate combines strong hardware design fundamentals with modern AI/ML-assisted ...
Senior Engineer I- Design
Chandler, AZ · On-site
... RTL design, functional verification, and contributing to next-generation mixed-signal and digital products. The ideal candidate combines strong hardware design fundamentals with modern AI/ML-assisted ...
In this role, you will be responsible for the design of System-on-Chip (SOC) solutions for wireless ... Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ...
In this role, you will be responsible for the design of System-on-Chip (SOC) solutions for wireless ... Proficient in RTL design (Verilog/System Verilog), Low-power design, synthesis, timing constraint ...
The successful candidate will play a central role in shaping scalable RTL-to-silicon methodologies ... Define top-level timing methodologies across IPs, subsystems, and full-chip integration to ensure ...
The successful candidate will play a central role in shaping scalable RTL-to-silicon methodologies ... Define top-level timing methodologies across IPs, subsystems, and full-chip integration to ensure ...
The successful candidate will play a central role in shaping scalable RTL-to-silicon methodologies ... Define top-level timing methodologies across IPs, subsystems, and full-chip integration to ensure ...
The successful candidate will play a central role in shaping scalable RTL-to-silicon methodologies ... Define top-level timing methodologies across IPs, subsystems, and full-chip integration to ensure ...
Ai Chip Design Rtl information
See Phoenix, AZ salary details
$79.9K - $89.1K
0% of jobs
$89.1K - $98.3K
0% of jobs
$98.3K - $107.5K
1% of jobs
$107.5K - $116.8K
0% of jobs
$116.8K - $126K
0% of jobs
$129.8K is the 25th percentile. Wages below this are outliers.
$126K - $135.2K
57% of jobs
$139.1K is the 75th percentile. Wages above this are outliers.
$135.2K - $144.4K
38% of jobs
$144.4K - $153.6K
0% of jobs
$153.6K - $162.8K
1% of jobs
$162.8K - $172K
1% of jobs
$172K - $181.2K
1% of jobs
$79.9K
$138.4K
$181.2K
How much do ai chip design rtl jobs pay per year?
As of Aug 12, 2026, the average yearly pay for ai chip design rtl in Phoenix, AZ is $138,380.00, according to ZipRecruiter salary data. Most workers in this role earn between $135,000.00 and $135,000.00 per year, depending on experience, location, and employer.
What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?
| Aspect | Ai Chip Design Rtl | Ai Chip Verification Engineer |
|---|---|---|
| Primary Focus | Developing and implementing Register Transfer Level (RTL) code for AI chips | Verifying and validating RTL designs to ensure functionality |
| Skills Required | HDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledge | Simulation, testbench creation, debugging, scripting skills |
| Work Environment | Design teams, hardware development labs, EDA tools | Verification teams, simulation environments, test setups |
| Certifications | Hardware design certifications, FPGA/ASIC training | Verification methodologies, UVM, SystemVerilog certifications |
While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.
What are common challenges faced by AI Chip Design RTL engineers during the verification process?
AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.
What is an AI Chip Design RTL engineer?
AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.
What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?
To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.
What are popular job titles related to Ai Chip Design Rtl jobs in Phoenix, AZ? For Ai Chip Design Rtl jobs in Phoenix, AZ, the most frequently searched job titles are:
What job categories do people searching Ai Chip Design Rtl jobs in Phoenix, AZ look for? The top searched job categories for Ai Chip Design Rtl jobs in Phoenix, AZ are:
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Re-posted 10 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 157 rated electronics manufacturers
Job description
Job Details:Job Description:
Intel is transforming from an Integrated Device Manufacturer (IDM) to a leading foundry service provider, offering world-class manufacturing capabilities to customers worldwide. Our Manufacturing Development and Customer Engineering (MDCE) organization is at the forefront of this transformation, focusing on yield improvement, performance optimization, and exceptional customer service delivery.
We are seeking a Principal Collateral Device Engineer to join our team within MDCE. This role requires regular onsite presence to fulfill essential job responsibilities and will creates next generation device and interconnect technology by ensuring the process device performance for developing processes is world class, using deep understanding of device physics.
Key Responsibilities:
Demonstrated expertise in leading cross functional group in defining derivative architectures including Design rules, transistors and interconnects. Expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture.
Experience in scribe line layout design and process monitoring structure development.
Proficiency in design rule development, validation, and waiver management processes.
Strong understanding of DTCO skills Including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration , Yield, Device and Design.
Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation.
Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs.
Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions.
Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization.
Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment.
Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Master's degree in Electrical Engineering, Physics, or related field
15+ years of experience in CMOS device engineering with focus on test chip design and device collateral development
Preferred Qualifications:
Ph.D. degree in Electrical Engineering, Physics, or related field
15+ years of experience in CMOS device engineering and collateral development
Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs
Experience with design rule checker (DRC) development and physical verification flows
Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures
Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization
Knowledge of mask generation including Boolean/OPC .
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $224,970.00-317,600.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968