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Ai Chip Design Rtl Jobs in Phoenix, AZ (NOW HIRING)

Accenture

AI Architect, Manager

Phoenix, AZ · On-site +1

$62.50 - $82.50/hr

Estimate, solution, design, and help drive and deliver AI deals. * Help build AI assets and enable ... Experience with AI (algorithms, AI-on-chip, AI hardware accelerators), Machine Learning (frameworks ...

Viasat, Inc.

FPGA Engineer (Space)

Tempe, AZ · On-site

$164.50K - $246.50K/yr

Own the architecture, design, and implementation of FPGA based digital systems * Develop RTL in ... Familiarity with AI Agents (e.g. Copilot, Claude, Cursor, etc.) * Strong troubleshooting skills

Viasat, Inc.

FPGA Engineer (Space)

Tempe, AZ

$164.50K - $246.50K/yr

Own the architecture, design, and implementation of FPGA based digital systems * Develop RTL in ... Familiarity with AI Agents (e.g. Copilot, Claude, Cursor, etc.) * Strong troubleshooting skills

Viasat

FPGA Engineer (Space)

Tempe, AZ

$164.50K - $246.50K/yr

Own the architecture, design, and implementation of FPGA based digital systems * Develop RTL in ... Familiarity with AI Agents (e.g. Copilot, Claude, Cursor, etc.) * Strong troubleshooting skills

Amat

Senior Workplace Design Manager

Phoenix, AZ · On-site +1

$116K - $159.50K/yr

... every new chip and advanced display in the world. We design, build and service cutting-edge ... our world - like AI and IoT. If you want to push the boundaries of materials science and ...

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How much do ai chip design rtl jobs pay per year?

As of May 28, 2026, the average yearly pay for ai chip design rtl in Phoenix, AZ is $138,380.00, according to ZipRecruiter salary data. Most workers in this role earn between $135,000.00 and $135,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an AI Chip Design RTL Engineer, and why are they important?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are some common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What are AI Chip Design RTL engineers?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What are popular job titles related to Ai Chip Design Rtl jobs in Phoenix, AZ? For Ai Chip Design Rtl jobs in Phoenix, AZ, the most frequently searched job titles are:
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Ai Chip Design Rtl jobs near you
Package Design Engineer

Package Design Engineer

Marvell Semiconductor, Inc.

Chandler, AZ

$131.20K/yr

Other

Life, Retirement

Posted yesterday

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Advanced Packaging Physical Design for Photonic Fabric BU

What You Can Expect

  • Package Design:
    • Lead Si/package/PCB/system co-design work collaborating with downstream system design teams and upstream ASIC designers to develop a portfolio of packages that meets a huge range of performance design points, while optimizing re-use in other Marvell products.
    • Scope all aspects of package design feasibility at Silicon interposer and substrate level for multi-chip SiP packaging.
    • Support pre/post silicon bring up, yield improvement activities, qualification, failure analysis, and system implementation.
  • Package Layout Expertise:
    • Lead all aspects of package layout based on I/O, SI-PI and form factor requirements, including routing, design for reliability, thermal, mechanical, manufacturability, bumping, substrate, material selection, assembly, and support for testing.
    • Meet specifications for high-speed interfaces such as HBM, DDR, PCIe and 56G/112G SerDes.
  • 2.5D and 3D Package Design Planning and Execution:
    • Plan and execute Silicon interposer and RDL based design layout solutions for advanced packaging architectures.
    • Netlist management for heterogeneous chiplet assemblies using latest EDA solutions.
  • Substrate Manufacturing and OSAT Assembly Engagement:
    • Supporting activities related to production and assembly of IC packages with substrate suppliers and OSATs.
    • Work with cross-functional teams and support package integration and architecture efforts with vendors.
    • Actively participate in qualification of package and board level assembly with sensitivity to physics of failures for high thermo-mechanical reliability, driving appropriate test vehicle definition and design.
    • Drive ideation and innovation of advanced package solutions and specifications with vendors to advance productization efforts by Marvell

What We're Looking For

  • Education:BS/MS/PhD in EE/ECE/MSE/ME/ChemE or related disciplines.
  • Experience:5-10 years of experience in Semiconductor Packaging Design of heterogeneous architectures, including silicon interposer and RDL designs.
  • Technical Expertise:
    • Extensive experience working with advanced packaging design tools such as Cadence APD.
    • Experience working with MCAD tools such as SolidWorks, AutoCAD and interconversion of package design databases to MCAD files.
    • Knowledge and insights to deliver high density/high performance interconnects in various 2.5D/3D packaging technologies including InFO, CoWoS, FoCoS and EMIB.
    • Good understanding of cross-functional packaging areas: Si floor plan, package, board layout and architecture, design rules, BOM, enabling material/process technologies, thermal, mechanical, Signal/Power Integrity, design for manufacturing, assembly, reliability, and cost.
    • Familiarity with photonics packaging is a plus but not necessary.
  • Substrate Vendor and OSAT Engagement:
    • Proven track record of working with substrate vendors to meet design for manufacturing, yield, and reliability.
    • Proven track record of engagement with OSATs to meet assembly requirements and drive new developments to meet new product requirements.
  • Industry Knowledge:Experience in High Speed Signaling best practices, Signal and Power integrity requirements.
  • Soft Skills:Strong analytical, problem-solving, cross-functional collaboration, project management, and technical presentation skills.

Expected Base Pay Range (USD)

166,520 - 249,500, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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