US_West | Network Design Engineer_L3
$102K - $140K/yr
Global Technical Skills Family : 6246 (T) Network operate & administration Technologies * Local Role Name : Digital Design (RTL) Engineer * Local Skills : Julie Skidmore * Languages Required:
61 Redolent Network Engineer Jobs Hiring Near You
US_West | Network Design Engineer_L3
$102K - $140K/yr
Global Technical Skills Family : 6246 (T) Network operate & administration Technologies * Local Role Name : Digital Design (RTL) Engineer * Local Skills : Julie Skidmore * Languages Required:
SRE Platform Engineer
Charlotte, NC · On-site
$55.75 - $74/hr
Configure and integrate platform components including compute, storage, and networking layers ... Engineering experience, or equivalent * Strong experience with Kubernetes, preferably OpenShift
SRE Platform Engineer
Charlotte, NC · On-site
$55.75 - $74/hr
Configure and integrate platform components including compute, storage, and networking layers ... Engineering experience, or equivalent * Strong experience with Kubernetes, preferably OpenShift
US_East | Network Design Engineer_L3
San Francisco, CA · On-site
$160K - $195K/yr
Global Technical Skills Family : 6246 (T) Network operate & administration Technologies * Local Role Name : Design Verification Engineer * Local Skills : Julie Skidmore * Languages Required:
US_East | Network Design Engineer_L3
San Francisco, CA · On-site
$160K - $195K/yr
Global Technical Skills Family : 6246 (T) Network operate & administration Technologies * Local Role Name : Design Verification Engineer * Local Skills : Julie Skidmore * Languages Required:
MDVT (Mechanical Design Verification Test Engineer)
Santa Clara, CA · On-site
$89K - $121K/yr
Mechanical Design Verification Test Engineer Location: Santa Clara, California Founded and funded ... centers, cloud networking, and cloud computing environments. Arista is building world-class ...
MDVT (Mechanical Design Verification Test Engineer)
Santa Clara, CA · On-site
$89K - $121K/yr
Mechanical Design Verification Test Engineer Location: Santa Clara, California Founded and funded ... centers, cloud networking, and cloud computing environments. Arista is building world-class ...
Senior Terraform Engineer (Hands-On) - Azure Platform, AI/ML & GenAI Work Authorization: GC & USC ... This is not an advisory role- you design, build, and ship : databases, AI/ML platforms, network ...
Senior Terraform Engineer (Hands-On) - Azure Platform, AI/ML & GenAI Work Authorization: GC & USC ... This is not an advisory role- you design, build, and ship : databases, AI/ML platforms, network ...
US_West | Data Engineer_L3
Anaheim, CA · On-site
... EPC core network. • Testing and validation of features such as LTE mobility management, SON ... hardware engineers to build network designs to solve connectivity problems. • Proactively ...
US_West | Data Engineer_L3
Anaheim, CA · On-site
... EPC core network. • Testing and validation of features such as LTE mobility management, SON ... hardware engineers to build network designs to solve connectivity problems. • Proactively ...
Wireless Engineer
Chandler, AZ · On-site
Currently seeking a Wireless Engineer for a 12+ month contract position located in Chandler, AZ ... Optimize network performance and troubleshoot connectivity issues * Ensure network security ...
Wireless Engineer
Chandler, AZ · On-site
Currently seeking a Wireless Engineer for a 12+ month contract position located in Chandler, AZ ... Optimize network performance and troubleshoot connectivity issues * Ensure network security ...
WLAN Solutions Engineer
San Diego, CA · On-site
Demonstrate how our AI/ML root-cause analysis reduces Mean Time to Innocence (MTTI) for network ... RF Engineering: Perform predictive designs (Ekahau/Hamina) and validation surveys. You are the ...
WLAN Solutions Engineer
San Diego, CA · On-site
Demonstrate how our AI/ML root-cause analysis reduces Mean Time to Innocence (MTTI) for network ... RF Engineering: Perform predictive designs (Ekahau/Hamina) and validation surveys. You are the ...
... especially networking and understanding root cause analysis. Enhancing design to prevent re ... Communicating with engineers is a part of the job. - Willing to dive into unfamiliar things.
... especially networking and understanding root cause analysis. Enhancing design to prevent re ... Communicating with engineers is a part of the job. - Willing to dive into unfamiliar things.
Android Engineer
San Bruno, CA · On-site
... mobile network clients using HTTP protocol, REST APIs and Google Cloud Messaging - Experience with Google Play APIs : Maps, Location, and Cloud Messaging - Experience with software debugging ...
Android Engineer
San Bruno, CA · On-site
... mobile network clients using HTTP protocol, REST APIs and Google Cloud Messaging - Experience with Google Play APIs : Maps, Location, and Cloud Messaging - Experience with software debugging ...
US_East | Platform Engineer - DevOps Specialist _L2
Santa Clara, CA · On-site
$62.25 - $85.25/hr
Linux kernel and networking protocols System experience, Network security, TCP/IP, DHCP, IPV4, IPV6 ... Embedded Engineer with cloud protocols expertise Named Job Posting? (if Yes - needs to be approved ...
US_East | Platform Engineer - DevOps Specialist _L2
Santa Clara, CA · On-site
$62.25 - $85.25/hr
Linux kernel and networking protocols System experience, Network security, TCP/IP, DHCP, IPV4, IPV6 ... Embedded Engineer with cloud protocols expertise Named Job Posting? (if Yes - needs to be approved ...
Android Engineer
Sunnyvale, CA · On-site
... mobile network clients using HTTP protocol, REST APIs and Google Cloud Messaging - Experience with Google Play APIs : Maps, Location, and Cloud Messaging - Experience with software debugging ...
Android Engineer
Sunnyvale, CA · On-site
... mobile network clients using HTTP protocol, REST APIs and Google Cloud Messaging - Experience with Google Play APIs : Maps, Location, and Cloud Messaging - Experience with software debugging ...
Automation Engineer (DevOps/Cloud)
Charlotte, NC · On-site
$51.50 - $70.50/hr
Automation Engineer (DevOps/Cloud) (26-06388) Location : Charlotte NC, (3 days in office, 2 days ... Solid understanding of Linux, shell scripting, networking fundamentals, and enterprise change ...
Automation Engineer (DevOps/Cloud)
Charlotte, NC · On-site
$51.50 - $70.50/hr
Automation Engineer (DevOps/Cloud) (26-06388) Location : Charlotte NC, (3 days in office, 2 days ... Solid understanding of Linux, shell scripting, networking fundamentals, and enterprise change ...
As a Release Triage Engineer, you will be responsible for triaging any networking/wifi/hdmi/BLE issues by retrieving and analyzing the data from the cloud, root causing the issue and raising it with ...
As a Release Triage Engineer, you will be responsible for triaging any networking/wifi/hdmi/BLE issues by retrieving and analyzing the data from the cloud, root causing the issue and raising it with ...
Software Engineer Embedded
Mountain View, CA · On-site
$155K - $204K/yr
... systems o Networking and protocol stacks o Middleware and services development o Automotive ... Programming skills in C/C++, with working knowledge of Rust
Software Engineer Embedded
Mountain View, CA · On-site
$155K - $204K/yr
... systems o Networking and protocol stacks o Middleware and services development o Automotive ... Programming skills in C/C++, with working knowledge of Rust
Sr. SRE Engineer (IAM focus)
Plano, TX · On-site
$54.50 - $72.50/hr
Position: Sr. SRE Engineer (IAM focus) (26-06661) Location: Plano, TX / Charlotte, NC / Pennington ... Strong background in Linux/Unix systems, networking, and security fundamentals. * Expertise in ...
Sr. SRE Engineer (IAM focus)
Plano, TX · On-site
$54.50 - $72.50/hr
Position: Sr. SRE Engineer (IAM focus) (26-06661) Location: Plano, TX / Charlotte, NC / Pennington ... Strong background in Linux/Unix systems, networking, and security fundamentals. * Expertise in ...
... network AC+DC simulation for low-voltage/high-current supplies. • Development of next generation memory interface considering Input/Output Physical Layer (IO PHY), SI/PI and physical design.
... network AC+DC simulation for low-voltage/high-current supplies. • Development of next generation memory interface considering Input/Output Physical Layer (IO PHY), SI/PI and physical design.
Android engineer - FT
Sunnyvale, CA · On-site
$66.50 - $87.25/hr
... mobile network clients using HTTP protocol, REST APIs and Google Cloud Messaging - Experience with Google Play APIs : Maps, Location, and Cloud Messaging - Experience with software debugging ...
Android engineer - FT
Sunnyvale, CA · On-site
$66.50 - $87.25/hr
... mobile network clients using HTTP protocol, REST APIs and Google Cloud Messaging - Experience with Google Play APIs : Maps, Location, and Cloud Messaging - Experience with software debugging ...
XFTBNJ Role: Wi-Fi Test and Automation Engineer Work location: Philadelphia, PA Background and Meet and Greet: MANDATORY "Strong experience (5-8+ years) in device testing, wireless networking or ...
XFTBNJ Role: Wi-Fi Test and Automation Engineer Work location: Philadelphia, PA Background and Meet and Greet: MANDATORY "Strong experience (5-8+ years) in device testing, wireless networking or ...
... Engineer will work as part of a highly interactive, cross functional team that is responsible for providing support for hardware, OS, software applications, and networking. Clearance: Active secret ...
... Engineer will work as part of a highly interactive, cross functional team that is responsible for providing support for hardware, OS, software applications, and networking. Clearance: Active secret ...
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US_West | Network Design Engineer_L3
Remote
Redolent, Inc.
• IT Services • 51 - 200 employees51 - 200 employees
$102K - $140K/yr
Contractor
Re-posted 28 days ago
Job description
Description:
Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.
Submit candidates under their legal name and use only Capgemini template
Candidate's photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.
In your submission include:
Phone #:
Email address:
Location (City and State):
Relocate:
Availability to start:
Visa type and expiration date:
Hiring Status: C2C/W2/1099QOpen for CTH (y/n):
Timeslots for Skype interview (provide Skype ID)
Due to additional onboarding requirements, a meet and greet is required for all new hires.
Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment.
If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to
Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.
Marie Samayoa
OBO Tactical Procurement | Procurement
Capgemini North America | Guatemala
Email: Marie.samayoa@capgemini.com
Job Description: Digital Design (RTL) Engineer
Location: Santa Clara, CA
Remote work option allowed
Required:
Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog
Experience in developing micro architectural document from requirements specifications
Experience developing designs from scratch
Experience applying linting and other (QC) quality checking and basic verification of designs.
Experience supporting SoC designers in integration as needed
Strong communication and collaboration skills
Preferred:
-Desirable but not essential experience: DMA, memory controller, MIPI DSI/CSI, data and control path pipeline design, interconnect and AMBA interfaces.
- Candidate with design automation, scripting experience (Python) is preferrable
• Develop HW architecture from specification documents.
• Take complete responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.
• Develop and execute low power design (UPF/CPF).
• Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc
• Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties)
• Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.
• Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.
• Take ownership of tasks and drive tasks to closure.
Synopsys/Cadence EDA Tools (Priority: 1)
LEC (Priority: 2)
STA/Constraints (Priority: 2)
Named Job Posting? (if Yes - needs to be approved by SCSC)
Additional Details
Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.
Submit candidates under their legal name and use only Capgemini template
Candidate's photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.
In your submission include:
Phone #:
Email address:
Location (City and State):
Relocate:
Availability to start:
Visa type and expiration date:
Hiring Status: C2C/W2/1099QOpen for CTH (y/n):
Timeslots for Skype interview (provide Skype ID)
Due to additional onboarding requirements, a meet and greet is required for all new hires.
Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment.
If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to
Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.
Marie Samayoa
OBO Tactical Procurement | Procurement
Capgemini North America | Guatemala
Email: Marie.samayoa@capgemini.com
Job Description: Digital Design (RTL) Engineer
Location: Santa Clara, CA
Remote work option allowed
Required:
Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog
Experience in developing micro architectural document from requirements specifications
Experience developing designs from scratch
Experience applying linting and other (QC) quality checking and basic verification of designs.
Experience supporting SoC designers in integration as needed
Strong communication and collaboration skills
Preferred:
-Desirable but not essential experience: DMA, memory controller, MIPI DSI/CSI, data and control path pipeline design, interconnect and AMBA interfaces.
- Candidate with design automation, scripting experience (Python) is preferrable
• Develop HW architecture from specification documents.
• Take complete responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.
• Develop and execute low power design (UPF/CPF).
• Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc
• Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties)
• Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.
• Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.
• Take ownership of tasks and drive tasks to closure.
Synopsys/Cadence EDA Tools (Priority: 1)
LEC (Priority: 2)
STA/Constraints (Priority: 2)
Named Job Posting? (if Yes - needs to be approved by SCSC)
Additional Details
- Global Grade : C
- Named Job Posting? (if Yes - needs to be approved by SCSC) : No
- Remote work possibility : (No Value)
- Global Role Family : 60239 (P) Cloud Infrastructure
- Global Technical Skills Family : 6246 (T) Network operate & administration Technologies
- Local Role Name : Digital Design (RTL) Engineer
- Local Skills : Julie Skidmore
- Languages Required: : English
About Redolent
Sourced by ZipRecruiter
Redolent, a dynamic and rapidly expanding company committed to excellence in software solutions, where success is fueled by a combination of technical expertise and efficient management practices. Our solutions create a measurable delta in our clients’ productivity and profitability, contributing to their growth and success.
Industry
It services
Company size
51 - 200 Employees
Headquarters location
San Jose, CA, US
Year founded
2008