17 Redolent Desktop Engineer Jobs Hiring Near You

Description:
Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.
Submit candidates under their legal name and use only Capgemini template
Candidate's photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.
In your submission include:
Phone #:
Email address:
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Hiring Status: C2C/W2/1099QOpen for CTH (y/n):
Timeslots for Skype interview (provide Skype ID)
Due to additional onboarding requirements, a meet and greet is required for all new hires.
Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment.
If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to
Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.
Marie Samayoa
OBO Tactical Procurement | Procurement
Capgemini North America | Guatemala
Email: Marie.samayoa@capgemini.com
Job Description: Post Silicon Validation Engineer
Location: San Jose, CA, Hybrid option allowed
Qualifications:
• BSEE, MSEE (or higher) preferred, in Electrical Engineering.
• Strong background in SOC/VLSI/Mixed Signal IC bring-up, production and characterization test, and product engineering.
• Strong fundamentals in IC design, Design for Test, and manufacturing concepts.
• Low level C, C++, RISV-V assembler, micro coding, Python, and familiarity with either Verilog, VHDL and SystemRDL
• Ability to debug hardware using lab equipment
• Knowledge of test cell integration and production test program release
• Proven understanding of the latest DFT and test solutions.
• Ability to thrive in a multifaceted environment
• High level of motivation and energy
Hands on experience with one or more of the following
• RISC-V
• Network On Chip IPs
• Memory Controller IPs (DDR5)
• Low power testing
• PCIe and CXL (testing)
• UCIe
• familiarity with FPGAs
• use of Logic Analyzer, scope and in general HW/FW integration and debugging
Roles/Responsibilities:
• Working with custom network processors, transceivers, mixed signal ICs, multi-die modules, bare die, and stacked die.
• Drive the post-silicon validation cycle to meet Product Quality and Time to Market Metrics. In a multi-function team, you will define and develop test plans for optimized test.
• Design and Develop testability requirements in close partnership with IP and design teams and influence implementation of test features.
• Craft test hardware, bring up test, and release test programs to production.
• Develop test requirements for ground-breaking IP, to minimize test overhead both in design and for production.
• Develop custom test solutions spanning high power, large dies, and packages to cost-sensitive products.
• Expertise with Advantest 93K to drive to lower test costs via optimized test implementation.
• Work closely with OSATs to set up test infrastructure as well as deploy test programs for production.
C/C++ (Priority: 2)
Python (Priority: 2)
Verilog/VHDL (Priority: 1)
Silicon Validation tools (Priority: 1)
Named Job Posting? (if Yes - needs to be approved by SCSC)
Additional Details

• Global Grade : C
• Named Job Posting? (if Yes - needs to be approved by SCSC) : No
• Remote work possibility : No
• Global Role Family : 60243 (P) Delivery Excellence
• Global Technical Skills Family : 6269 (T) Office / Desktop Solutions
• Local Role Name : Post Silicon Validation Engineer
• Local Skills : Julie Skidmore
• Languages Required: : English