IC/RTL Design Engineer
San Jose, CA · On-site
Write block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before ... Collaborate with the architecture, modelling, DV, DFT, and backend teams as your blocks move ...
11 Sva Back End Developer Jobs Hiring Near You
IC/RTL Design Engineer
San Jose, CA · On-site
Write block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before ... Collaborate with the architecture, modelling, DV, DFT, and backend teams as your blocks move ...
Write block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before ... Collaborate with the architecture, modelling, DV, DFT, and backend teams as your blocks move ...
Write block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before ... Collaborate with the architecture, modelling, DV, DFT, and backend teams as your blocks move ...
SoC Design Engineer
Santa Clara, CA · On-site
Work closely with back-end teams on floorplanning, timing closure, static timing analysis (STA ... Develop verification environments and models using SystemVerilog, SVA, Python, and Perl, and ...
Quick apply
SoC Design Engineer
Santa Clara, CA · On-site
Work closely with back-end teams on floorplanning, timing closure, static timing analysis (STA ... Develop verification environments and models using SystemVerilog, SVA, Python, and Perl, and ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Work closely with back-end teams on floorplanning, timing closure, static timing analysis (STA ... Develop verification environments and models using SystemVerilog, SVA, Python, and Perl, and ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Work closely with back-end teams on floorplanning, timing closure, static timing analysis (STA ... Develop verification environments and models using SystemVerilog, SVA, Python, and Perl, and ...
SoC Design Engineer
$156K - $160K/yr
Work closely with back-end teams on floorplanning, timing closure, static timing analysis (STA ... Develop verification environments and models using SystemVerilog, SVA, Python, and Perl, and ...
SoC Design Engineer
$156K - $160K/yr
Work closely with back-end teams on floorplanning, timing closure, static timing analysis (STA ... Develop verification environments and models using SystemVerilog, SVA, Python, and Perl, and ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Work closely with back-end teams on floorplanning, timing closure, static timing analysis (STA ... Develop verification environments and models using SystemVerilog, SVA, Python, and Perl, and ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Work closely with back-end teams on floorplanning, timing closure, static timing analysis (STA ... Develop verification environments and models using SystemVerilog, SVA, Python, and Perl, and ...
Writing and verifying SystemVerilog Assertions (SVA) for a design * Writing timing constraints and ... backend, system and test engineering teams * Post-Si bring-up, validation and debugging ...
Quick apply
Writing and verifying SystemVerilog Assertions (SVA) for a design * Writing timing constraints and ... backend, system and test engineering teams * Post-Si bring-up, validation and debugging ...
IP Integration Engineer
$175K - $311K/yr
... back-end design teams for integrating the IP Preferred Qualifications Experience with Verilog ... Experience writing Verilog, SystemVerilog, SVA hardware description languages Minimum ...
IP Integration Engineer
$175K - $311K/yr
... back-end design teams for integrating the IP Preferred Qualifications Experience with Verilog ... Experience writing Verilog, SystemVerilog, SVA hardware description languages Minimum ...
IP Integration Engineer
$175K - $311K/yr
... back-end design teams for integrating the IP Preferred Qualifications Experience with Verilog ... Experience writing Verilog, SystemVerilog, SVA hardware description languages Minimum ...
IP Integration Engineer
$175K - $311K/yr
... back-end design teams for integrating the IP Preferred Qualifications Experience with Verilog ... Experience writing Verilog, SystemVerilog, SVA hardware description languages Minimum ...
RTL Design Lead/IC Front-End Architect/Datapath Lead
San Jose, CA · On-site
$64.75 - $88.75/hr
You'll work alongside a team of world-class engineers solving some of the hardest challenges in ... Establish designer-level verification: block-level testbenches/sanity checks and assertion (SVA ...
RTL Design Lead/IC Front-End Architect/Datapath Lead
San Jose, CA · On-site
$64.75 - $88.75/hr
You'll work alongside a team of world-class engineers solving some of the hardest challenges in ... Establish designer-level verification: block-level testbenches/sanity checks and assertion (SVA ...
RTL Design Lead/IC Front-End Architect/Datapath Lead
$64.75 - $88.75/hr
You'll work alongside a team of world-class engineers solving some of the hardest challenges in ... Establish designer-level verification: block-level testbenches/sanity checks and assertion (SVA ...
RTL Design Lead/IC Front-End Architect/Datapath Lead
$64.75 - $88.75/hr
You'll work alongside a team of world-class engineers solving some of the hardest challenges in ... Establish designer-level verification: block-level testbenches/sanity checks and assertion (SVA ...
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Full-time
Re-posted 26 days ago
Job description
IC/RTL Design Engineer/ Front-End Engineer
About the role. You design and implement the digital front-end RTL at the heart of the chip - including the high-speed datapath that moves data between UCIe and the optical front end. Guided by the interface specs and coding standards, you take blocks from micro-architecture through clean, timing-aware RTL and block-level verification. It's a hands-on role with room to grow your scope as the team and the chip mature.
What you'll do
Required
Preferred
About the role. You design and implement the digital front-end RTL at the heart of the chip - including the high-speed datapath that moves data between UCIe and the optical front end. Guided by the interface specs and coding standards, you take blocks from micro-architecture through clean, timing-aware RTL and block-level verification. It's a hands-on role with room to grow your scope as the team and the chip mature.
What you'll do
- Develop block-level micro-architecture for your assigned blocks, and contribute to interface and register definitions.
- Design and implement front-end RTL blocks in SystemVerilog - datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.
- Integrate IP and support parameterization for configurability.
- Write clean, lint-clean, CDC/RDC-clean RTL that follows the coding and quality standards.
- Write block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before handoff to DV.
- Power- and timing-aware design - managing block activity, clock-gating, pipelining, and retiming; partner with the backend team on physical closure for your blocks.
- Bring-up and debug across simulation and emulation / FPGA prototyping; support DV and silicon bring-up, including DFT/debug hooks in your blocks.
- Collaborate with the architecture, modelling, DV, DFT, and backend teams as your blocks move through the flow.
Required
- BS or MS in Electrical/Computer Engineering (or equivalent experience).
- 3+ years of digital RTL design in SystemVerilog, with blocks taken from micro-architecture through to verification handoff.
- Solid digital design fundamentals: pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI).
- Lint and CDC/RDC discipline and clean-RTL practices.
- Power- and timing-aware design practices; comfort with synthesis and timing closure, working with the backend team.
- Strong debug skills in simulation; scripting in Python, Perl, or TCL.
Preferred
- High-speed datapath, SerDes-adjacent, or interface design exposure (UCIe, PCIe/CXL, or similar).
- FEC/coding datapath familiarity (e.g., Reed-Solomon) and gray-code mapping.
- Assertion-based verification (SVA) and familiarity with UVM block-level testbenches; emulation / FPGA prototyping experience.
- Exposure to scale-up / scale-out interconnects or network switch / NIC / memory-controller datapaths.
- Low-power / UPF and DFT (scan) concepts.
- Optical transceiver, CPO, or linear-drive optics background; advanced-node (N5/N3/N2) design experience.