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Yield Analysis Engineer Jobs (NOW HIRING)

Nokia

Senior Photonic Yield Engineer

Manhattan, NY

$114K - $157K/yr

You will oversee a fleet of test equipment and work with engineers and operators at our Fab and ... Strong proficiency in wafer scale yield analysis: experience creating and reviewing Pareto charts ...

onsemi

Yield and Device Engineering Manager

Hopewell, NY · On-site

$127K - $217K/yr

The Yield, Device, and Integration Engineering Manager leads a multidisciplinary organization of ... Manage a team responsible for analyzing electrical test data-including inline parametric results ...

hyve solutions

Failure Analysis Engineer

Fremont, CA · On-site

... yield. * Collaborate with suppliers to investigate component-level failures and improve incoming ... failure analysis, hardware validation, quality engineering, reliability engineering, or ...

Hyve Solutions

Failure Analysis Engineer

Fremont, CA · On-site

$142K - $169K/yr

... yield. * Collaborate with suppliers to investigate component-level failures and improve incoming ... failure analysis, hardware validation, quality engineering, reliability engineering, or ...

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Yield Analysis Engineer information

See salary details

$45.5K

$93.2K

$135.5K

How much do yield analysis engineer jobs pay per year?

As of Jul 13, 2026, the average yearly pay for yield analysis engineer in the United States is $93,179.00, according to ZipRecruiter salary data. Most workers in this role earn between $70,000.00 and $118,000.00 per year, depending on experience, location, and employer.

What are Yield Analysis Engineers?

Yield Analysis Engineers are professionals who focus on analyzing and improving the manufacturing yield of products, particularly in industries like semiconductor fabrication. They collect and interpret process data to identify patterns, root causes of yield loss, and opportunities for process optimization. Their work helps companies maximize production efficiency and minimize defects, ultimately reducing costs and increasing profitability. Yield Analysis Engineers collaborate with cross-functional teams, including manufacturing, quality assurance, and process engineering, to implement solutions that improve yield.

What is the difference between Yield Analysis Engineer vs Process Engineer?

AspectYield Analysis EngineerProcess Engineer
Primary FocusAnalyzing and improving manufacturing yields through data analysisDesigning, implementing, and optimizing manufacturing processes
Skills & CertificationsData analysis, statistical tools, engineering fundamentalsProcess design, engineering principles, certifications like Six Sigma
Work EnvironmentManufacturing plants, R&D labs, data analysis teamsProduction floors, process development departments

While both roles are integral to manufacturing, Yield Analysis Engineers focus on analyzing yield data to identify issues and improve output, whereas Process Engineers develop and optimize manufacturing processes. Both roles require strong analytical skills and engineering knowledge, often working closely to enhance production efficiency.

How does a Yield Analysis Engineer typically collaborate with cross-functional teams to address manufacturing issues?

Yield Analysis Engineers regularly work alongside process engineers, product engineers, and quality assurance teams to identify and resolve manufacturing bottlenecks or defects. They analyze data from production lines, share findings with relevant teams, and participate in root cause analyses to implement corrective actions. This collaborative approach ensures that yield improvements are based on comprehensive insights and that solutions are effectively integrated into existing workflows. Strong communication and teamwork skills are essential in this role, as addressing yield challenges often requires input from multiple technical disciplines.

What are the key skills and qualifications needed to thrive as a Yield Analysis Engineer, and why are they important?

To thrive as a Yield Analysis Engineer, you need a solid background in electrical engineering, semiconductor manufacturing, and data analysis, typically supported by a relevant engineering degree. Experience with statistical analysis tools (like JMP or Minitab), data visualization software, and familiarity with yield management systems are commonly required. Strong problem-solving abilities, attention to detail, and effective communication skills help you identify issues and collaborate with cross-functional teams. These skills are crucial for optimizing manufacturing processes, reducing defects, and ensuring high product yield in a competitive semiconductor industry.
More about Yield Analysis Engineer jobs
What cities are hiring for Yield Analysis Engineer jobs? Cities with the most Yield Analysis Engineer job openings:
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Yield Analysis Engineer jobs near you
Infographic showing various Yield Analysis Engineer job openings in the United States as of July 2026, with employment types broken down into 87% Full Time, 11% Part Time, and 2% Contract. Highlights an 83% Physical, 3% Hybrid, and 14% Remote job distribution, with an average salary of $93,179 per year, or $44.8 per hour.
Product Development Engineer - Scan Diagnostics

Product Development Engineer - Scan Diagnostics

Intel

Hillsboro, OR

$141K - $269K/yr

Full-time

Medical, Retirement, PTO

Posted 27 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 146 frontline employees who took The Breakroom Quiz

11th of 142 rated electronics manufacturers

Job description

Job Details:Job Description: 

The Role and Impact
As a Product Development Engineer - Scan Diagnostics, you will play a core role in shaping Intel's product innovation and manufacturing excellence. Your efforts will be pivotal in transforming cutting-edge integrated circuits from design feasibility to high-volume production. This role offers exceptional learning and growth opportunities, providing broad exposure to the entire semiconductor product lifecycle, from initial definition to HVM. By collaborating with cross-functional teams, you will influence product design, ensure seamless production ramp-up, and directly contribute to delivering world-class solutions to Intel's customers. You'll engage in advanced diagnostic techniques for fault identification and yield improvement, collaborating with stakeholders across the company and our supplier ecosystem.
Key Responsibilities

  • Create, Enable and Support Scan/Chain Diagnosis infrastructure and processes for Intel's HVM products.

  • Support fail-based and volume diagnostic analysis and yield analysis requests to drive continuous yield improvement.

  • Support CAD infrastructure and computational resources for Diagnostics across all HVM product lines.

  • Develop and optimize tools, methods, and flows for Design for Test (DFT), diagnostics, and yield analysis.

  • Collaborate with external vendors and internal teams to establish standard industry practices for diagnostics and yield analysis.

  • Maintain relationships with Electronic Design Automation (EDA) vendors to access the latest tools and methodologies.

  • Facilitate knowledge transfer to ensure Yield Management and Failure Analysis team members are updated with the latest methodologies and tools.

  • Define and monitor DFX quality metrics (coverage, test cost, and debuggability) from development to production ramp-up.

  • Work closely with Design and New Product Introduction (NPI) teams to ensure diagnostic readiness for new products.

Qualifications:

Minimum Qualifications:

  • Candidate must possess at least a bachelor's degree in engineering or related field. Master's degree or Ph.D. preferred.

  • 4+ years of experience in DFT, Scan Diagnostics enablement, Post-Si diagnostics debug, Yield Analysis, and/or EDA tools.

  • Proficiency in at least one of the following: Python, TCL, C-Shell, or PERL scripting.

  • Seeking candidates with strong communication and teamwork skills.

Preferred Qualifications:

  • Experience with Siemens's Tessent Test and Yield Analysis tools or similar.

  • Experience with Synopsys's Yield Explorer or similar tools.

  • Experience with SOC / IP DFT control architecture (e.g., JTAG, IJTAG, IEEE1500).

  • Experience in Custom and/or ASIC circuit design.

We are looking for innovators and problem-solvers to join our team and help us continue to redefine the future of technology. If you are passionate about making an impact and growing your career in a dynamic and collaborative environment, apply now.

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroBusiness group:The Corporate Planning Group (CPG) is the strategic heartbeat of Intel, acting as catalyst for innovation and transformation, guiding the company towards achieving its vision and maintaining a competitive edge in the marketplace. CPG exists to build a comprehensive operating plan that leverages internal and external manufacturing for Intel's growth. We emphasize data-driven innovation and results, ensuring we meet customer demands and financial targets. Join CPG to be part of a forward-looking group that is not just planning for tomorrow, but redefining it.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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