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Vlsi Design Verification Engineer Jobs in Phoenix, AZ

Cirrus Logic

Design Verification Engineer

Chandler, AZ · On-site

$133.90K - $163.50K/yr

We are seeking an experienced and innovative Design Verification Engineer to join a world-class silicon design verification team. This role partners closely with digital and analog designers, systems ...

Cirrus Logic

Senior Design Verification Engineer

Chandler, AZ · On-site

$133.90K - $163.50K/yr

We are seeking an experienced and innovative Design Verification Engineer to join a world-class silicon design verification team. This role partners closely with digital and analog designers, systems ...

Cirrus Logic

Staff Design Verification Engineer

Chandler, AZ · On-site

$133.90K - $163.50K/yr

We are seeking an experienced and innovative Design Verification Engineer to join a world-class silicon design verification team. This role partners closely with digital and analog designers, systems ...

Intel

Senior CPU Design Verification Engineer

Phoenix, AZ

$135K - $164.80K/yr

What You'll Do As a Senior CPU Design Verification Engineer you will play a critical role in ensuring architectural correctness, functional robustness, and powerefficient performance of Intel's Atom ...

Cirrus Logic

Senior Design Verification Engineer

Chandler, AZ · On-site

$133.90K - $163.50K/yr

Join our silicon design verification team and work closely with digital/analog designers, applications engineers, and manufacturing test, participating in all aspects of verification for complete ...

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How much do vlsi design verification engineer jobs pay per year?

As of May 27, 2026, the average yearly pay for vlsi design verification engineer in Phoenix, AZ is $139,760.00, according to ZipRecruiter salary data. Most workers in this role earn between $127,400.00 and $155,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a VLSI Design Verification Engineer, and why are they important?

To thrive as a VLSI Design Verification Engineer, you need a solid background in digital logic design, computer architecture, and verification methodologies, typically supported by a degree in electrical engineering or a related field. Proficiency with hardware description languages like Verilog or VHDL, simulation tools such as ModelSim or Synopsys VCS, and familiarity with UVM or SystemVerilog are commonly required. Strong analytical thinking, attention to detail, and effective communication are crucial soft skills for identifying design flaws and collaborating with cross-functional teams. These skills and qualifications ensure accurate, reliable chip designs and efficient project execution in the competitive semiconductor industry.

What are some common challenges faced by VLSI Design Verification Engineers during the verification process?

VLSI Design Verification Engineers often encounter challenges such as managing increasingly complex system-on-chip (SoC) designs, ensuring thorough test coverage, and debugging intricate functional issues. Coordinating with cross-functional teams—like design, software, and validation—is essential to align test plans and resolve ambiguities quickly. Additionally, keeping up with evolving verification methodologies and tools (such as UVM or SystemVerilog) requires a commitment to continuous learning, but offers strong career growth opportunities for those who master them.

What is a VLSI Design Verification Engineer?

A VLSI Design Verification Engineer is a specialist responsible for ensuring that integrated circuits (ICs) and systems-on-chip (SoCs) meet their design specifications before manufacturing. They use various verification methodologies, such as simulation, formal verification, and hardware emulation, to identify and fix functional errors in digital designs. Their role is critical in the semiconductor industry to ensure product quality, reduce costly re-spins, and speed up time-to-market. They often work closely with design engineers, using tools like SystemVerilog, UVM, and other verification frameworks.

What is the difference between Vlsi Design Verification Engineer vs Vlsi Design Engineer?

AspectVlsi Design Verification EngineerVlsi Design Engineer
Primary FocusVerifying the correctness of VLSI designs through testing and simulationCreating and implementing VLSI chip designs and architectures
Skills & CertificationsHardware description languages (HDL), verification tools, scripting, knowledge of verification methodologiesHDL, digital design, synthesis, timing analysis, and physical design skills
Work EnvironmentDesign teams, verification labs, simulation environmentsDesign teams, synthesis and implementation tools, physical design environments

While both roles require HDL knowledge and work within VLSI teams, the Vlsi Design Verification Engineer primarily focuses on testing and validating designs, whereas the Vlsi Design Engineer is responsible for creating and implementing the actual chip designs.

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Vlsi Design Verification Engineer jobs near you
Design Verification Engineer

Design Verification Engineer

Cirrus Logic

Chandler, AZ • On-site

$133.90K - $163.50K/yr

Full-time

Posted 13 days ago

Job description

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn't do it without our extraordinary workforce - and that's where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!
We are seeking an experienced and innovative Design Verification Engineer to join a world-class silicon design verification team. This role partners closely with digital and analog designers, systems and applications engineers, firmware/software teams, and manufacturing test to deliver high-quality mixed-signal IC solutions. You will be responsible for end-to-end functional verification across block-level and chip-level designs, contributing to advanced verification methodologies and infrastructure.
This position offers exposure to multiple verification domains including UVM-based testbench development, formal verification, hardware emulation/acceleration, gate-level simulations, and software-driven verification in a highly collaborative and technically rigorous environment.
Responsibilities:
  • Develop comprehensive verification plans aligned with design and system requirements.
  • Perform functional verification of custom mixed-signal ASICs at block and chip level.
  • Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions.
  • Create directed and constrained-random test suites to ensure robust functional coverage.
  • Implement, analyze, and drive functional and code coverage, including coverage closure.
  • Conduct failure analysis, regression triage, and debug, resolving functional and timing-related issues.
  • Run and debug gate-level simulations, including timing violations and back-annotation issues.
  • Develop and maintain digital and mixed-signal behavioral models to support verification.
  • Support verification flow and infrastructure development, including regressions and automation.
  • Collaborate cross-functionally with digital/analog design, systems, applications, firmware/software, and manufacturing test teams.
  • Contribute to both pre-silicon verification and post-silicon validation efforts.
  • Proactively improve verification methodologies, processes, and best practices.

Required Knowledge, Skills, and Experience:
  • Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.
    • Bachelor's with 2+ years of relevant experience.
    • Master's with 0+ years of relevant experience.
  • Significant industry experience in silicon design and/or ASIC verification.
  • Strong proficiency with HDLs: Verilog and/or VHDL.
  • Strong proficiency with HVLs: SystemVerilog with UVM (or OVM/AVM/Vera).
  • Solid understanding of digital design principles and system architecture.
  • Hands-on experience with:
    • Testbench architecture and stimulus generation
    • Regression execution and debug
    • Coverage analysis and closure
  • Ability to work effectively in a cross-disciplinary, team-oriented environment.

Preferred Knowledge, Skills, and Experience:
  • Experience verifying mixed-signal ASICs in complex SoC environments.
  • Knowledge of signal processing concepts relevant to mixed-signal designs.
  • Experience with SystemVerilog Assertions (SVA).
  • Exposure to or hands-on experience with:
    • Formal verification
    • Hardware emulation or acceleration
    • Software-driven verification
  • Demonstrated ability to evaluate, debug, and improve verification flows and methodologies.

#LI-Hybrid
#LI-EK1
#HOTT
Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role.
Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.

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