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Vlsi Design Verification Engineer Jobs in Virginia

You will own critical interfaces, system error budgets, configuration management, and verification ... message-design interfaces. Own configuration management for the program and the technical ...

Sr. Thermal Engineer

Arlington, VA · On-site

$120K - $165K/yr

Overview The Senior Thermal Engineer position is a full-time exempt position. The individual will ... to support hardware design verification and system performance analysis. * Assess thermal ...

Sr. Thermal Engineer

Arlington, VA · On-site

$120K - $165K/yr

Overview The Senior Thermal Engineer position is a full-time exempt position. The individual will ... to support hardware design verification and system performance analysis. * Assess thermal ...

Sr. Thermal Engineer

Arlington, VA · On-site

$120K - $165K/yr

Overview The Senior Thermal Engineer position is a full-time exempt position. The individual will ... to support hardware design verification and system performance analysis. * Assess thermal ...

Principal Software Engineer

Ashburn, VA · On-site

$138K - $185K/yr

  • Medical

  • Retirement

  • PTO

Principal Software Engineer - Onsite Ashburn, VA or Massachusetts We are looking for creative ... Hardware design verification test development * Firmware and/or BIOS development * Proven ...

Principal Software Engineer

Ashburn, VA · On-site

$138K - $185K/yr

  • Medical

  • Retirement

  • PTO

Principal Software Engineer - Onsite Ashburn, VA or Massachusetts We are looking for creative ... Hardware design verification test development * Firmware and/or BIOS development * Proven ...

Mechanical Design Engineer

Chesterfield, VA · On-site

$72K - $97K/yr

Mechanical Design Engineer Schedule: 9/80 schedule (every other Friday off) Primary Location ... Verify equipment meets customer specifications, engineering standards, and regulatory requirements.

New

Mechanical Design Engineer

Chesterfield, VA · On-site

$72K - $97K/yr

Mechanical Design Engineer Schedule: 9/80 schedule (every other Friday off) Primary Location ... Verify equipment meets customer specifications, engineering standards, and regulatory requirements.

New

Quality Engineer I

Virginia Beach, VA

$64K - $83K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Quality Engineering Schedule : Monday-Friday | 8:15AM - 5:00PM Clinical Status : Clinical HOW YOU ... This role will also play a critical role in risk management, design verification and validation (V ...

... a Design Engineer to join our Critical Infrastructure Protection team supporting priority ... Systems Integration & Testing Develop strategies to test and verify electronic security systems and ...

Quality Engineer I

Virginia Beach, VA · On-site

$68K - $88K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Quality Engineering Schedule: Monday-Friday 8:15AM - 5:00PM Clinical Status: Clinical HOW YOU'LL ... This role will also play a critical role in risk management, design verification and validation (V ...

Quality Engineer I

Virginia Beach, VA · On-site

$68K - $88K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Quality Engineering Schedule: Monday-Friday | 8:15AM - 5:00PM Clinical Status: Clinical HOW YOU'LL ... This role will also play a critical role in risk management, design verification and validation (V ...

Hardware Design Engineer

Arlington, VA · On-site

$87K - $157K/yr

  • Medical

  • Retirement

  • PTO

This role will also support integration, test, and verification in the final products. This ... design team (electrical engineers, systems engineers and scientists) to design and integrate ...

Showing results 41-60

Vlsi Design Verification Engineer information

See Virginia salary details

$104.6K

$147.9K

$165.6K

How much do vlsi design verification engineer jobs pay per year?

As of Aug 17, 2026, the average yearly pay for vlsi design verification engineer in Virginia is $147,870.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,800.00 and $164,600.00 per year, depending on experience, location, and employer.

What is a VLSI design verification engineer?

A VLSI Design Verification Engineer is a specialist responsible for ensuring that integrated circuits (ICs) and systems-on-chip (SoCs) meet their design specifications before manufacturing. They use various verification methodologies, such as simulation, formal verification, and hardware emulation, to identify and fix functional errors in digital designs. Their role is critical in the semiconductor industry to ensure product quality, reduce costly re-spins, and speed up time-to-market. They often work closely with design engineers, using tools like SystemVerilog, UVM, and other verification frameworks.

What are the key skills and qualifications needed to thrive as a VLSI design verification engineer?

To thrive as a VLSI Design Verification Engineer, you need a solid background in digital logic design, computer architecture, and verification methodologies, typically supported by a degree in electrical engineering or a related field. Proficiency with hardware description languages like Verilog or VHDL, simulation tools such as ModelSim or Synopsys VCS, and familiarity with UVM or SystemVerilog are commonly required. Strong analytical thinking, attention to detail, and effective communication are crucial soft skills for identifying design flaws and collaborating with cross-functional teams. These skills and qualifications ensure accurate, reliable chip designs and efficient project execution in the competitive semiconductor industry.

What are some common challenges faced by VLSI design verification engineers during the verification process?

VLSI Design Verification Engineers often encounter challenges such as managing increasingly complex system-on-chip (SoC) designs, ensuring thorough test coverage, and debugging intricate functional issues. Coordinating with cross-functional teams—like design, software, and validation—is essential to align test plans and resolve ambiguities quickly. Additionally, keeping up with evolving verification methodologies and tools (such as UVM or SystemVerilog) requires a commitment to continuous learning, but offers strong career growth opportunities for those who master them.

What is the difference between Vlsi Design Verification Engineer vs Vlsi Design Engineer?

AspectVlsi Design Verification EngineerVlsi Design Engineer
Primary FocusVerifying the correctness of VLSI designs through testing and simulationCreating and implementing VLSI chip designs and architectures
Skills & CertificationsHardware description languages (HDL), verification tools, scripting, knowledge of verification methodologiesHDL, digital design, synthesis, timing analysis, and physical design skills
Work EnvironmentDesign teams, verification labs, simulation environmentsDesign teams, synthesis and implementation tools, physical design environments

While both roles require HDL knowledge and work within VLSI teams, the Vlsi Design Verification Engineer primarily focuses on testing and validating designs, whereas the Vlsi Design Engineer is responsible for creating and implementing the actual chip designs.

What job categories do people searching Vlsi Design Verification Engineer jobs in Virginia look for?

The top searched job categories for Vlsi Design Verification Engineer jobs in Virginia are:

What cities in Virginia are hiring for Vlsi Design Verification Engineer jobs?

Cities in Virginia with the most Vlsi Design Verification Engineer job openings:

Infographic showing various Vlsi Design Verification Engineer job openings in Virginia as of August 2026, with employment types broken down into 59% Full Time, and 41% Contract. Highlights an 80% In-person, and 20% Remote job distribution, with an average salary of $147,870 per year, or $71.1 per hour.

Principal Systems Engineer

TalentRemedy

Herndon, VA

Full-time

Posted 10 days ago


Job description

An aerospace client is seeking a full-time Systems Chief Engineer to lead integration across their satellite, payload, ground, RF, timing, and software systems. You will own critical interfaces, system error budgets, configuration management, and verification closure, ensuring multiple satellite generations come together as one cohesive, flight-ready constellation. Responsibilities: Own the whole-of-system error budget across satellite generations, ensuring subsystem-level performance rolls up to a coherent, verifiable system that closes as a whole rather than as individually optimized subsystems.

Own and maintain the program's critical interface control documents, including payload-to-bus, ground-to-payload, and LEONS-to-MOS interfaces, as well as mixed-constellation user range accuracy and message-design interfaces. Own configuration management for the program and the technical relationship with the spacecraft bus vendor, including interface definition, design-review participation, and change control. Drive execution through the broader engineering team - directing the PNT budget owner, timing scientist, RF link-budget owners, Integration and Test Engineer, and Timing Verification Engineer to produce the verification evidence you integrate into system-level closure.

Operate across every technical pillar within Space Systems - payload, bus, ground, RF, timing, software, and verification - serving as the primary systems-integration authority during this phase of program growth and taking the highest-leverage technical integration workload off the Director of Space Systems. Identify system-level risks early, assign clear technical ownership, drive decisions to closure, and ensure that requirements, interfaces, budgets, and verification evidence remain aligned as the architecture evolves. Requirements 12+ years of systems engineering experience at the principal, lead, or chief-engineer level, with responsibility spanning spacecraft payloads, ground systems, satellite buses, or similarly complex integrated systems.

Demonstrated experience owning and closing system-level error budgets, technical interfaces, and verification activities across multiple interfacing subsystems. Proven ability to drive technical execution and verification closure across peer organizations and teams you do not directly manage. The technical credibility, judgment, and influence required to resolve cross-functional issues, establish alignment, and hold owners accountable for system-level outcomes.

Direct experience developing, managing, and maintaining interface control documents on an active development or flight program. Strong understanding of requirements decomposition, technical risk management, configuration management, and system-level trade studies. Must be a U.S

Person. Desired: Experience establishing or scaling systems-engineering practices for a program growing from tens to hundreds of spacecraft. Constellation-scale systems thinking, including the ability to account for configuration variability, production cadence, fleet performance, interoperability, and long-term verification needs.

Experience with Global Navigation Satellite Systems, positioning, navigation and timing, precision timing, or related mission architectures. Experience supporting multiple hardware generations or vehicle configurations in parallel while maintaining architectural consistency and configuration discipline. Familiarity with ground-segment or mission-operations architectures.