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Verification And Validation Engineer Jobs in Oregon

K2 Space

OR · On-site

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

Drive constrained-random and directed testing strategies to validate functionality, corner cases ... verification partners when needed. Qualifications * B.S. or M.S. in Electrical Engineering ...

Intel

CPU Verification Engineer

Hillsboro, OR · On-site

$148K/yr

  • Medical

  • Retirement

  • PTO

Develop and execute sophisticated verification plans to validate CPU logic against architectural ... Partner closely with CPU architects, RTL developers, and physical design teams to verify complex ...

Intel

CPU Verification Engineer

Hillsboro, OR · On-site

$105K - $200K/yr

  • Medical

  • Retirement

  • PTO

No one else is obsessed with engineering and has a brighter future. Every day, we create world ... Develop and execute comprehensive verification plans to validate CPU logic against architectural ...

Intel

SoC Verification Engineer

Hillsboro, OR · On-site

$141K - $200K/yr

  • Medical

  • Retirement

  • PTO

Position Overview As a SoC Design Verification Engineer, you will play a pivotal role in ensuring ... Experience with postsilicon validation and incorporating feedback into presilicon test plans

Intel

Senior CPU Verification Engineer

Hillsboro, OR · On-site

$141K - $269K/yr

  • Medical

  • Retirement

  • PTO

No one else is obsessed with engineering and has a brighter future. Every day, we create world ... Lead, drive, develop and execute comprehensive verification plans to validate CPU logic against ...

Nvidia

OR · Hybrid

Own validation of Clocking structures in Tegra and GPU products from start to finish, including ... Hands on experience in object-oriented programming * Prior design or verification experience at the ...

Intel

IP Design Verification Engineer

Hillsboro, OR · On-site

$141K - $200K/yr

  • Medical

  • Retirement

  • PTO

Join Intel as a Mixed Signal Design Verification Engineer and play a critical role in shaping the ... Perform analog behavioral modeling to validate design functionality, timing, and power objectives.

Apple

Emulation Verification Engineer

Beaverton, OR

$141K - $172K/yr

... Validation, Power and SW teams to bring up large SoCs on emulation platform - Develop/apply ... Design and verification that aids with emulation activities, using Verilog/System Verilog/UVM ...

Apple

Emulation Verification Engineer

Beaverton, OR

$141K - $172K/yr

... Validation, Power and SW teams to bring up large SoCs on emulation platform - Develop/apply ... Design and verification that aids with emulation activities, using Verilog/System Verilog/UVM ...

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Verification And Validation Engineer information

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How much do verification and validation engineer jobs pay per hour?

As of Aug 13, 2026, the average hourly pay for verification and validation engineer in Oregon is $54.98, according to ZipRecruiter salary data. Most workers in this role earn between $41.68 and $66.83 per hour, depending on experience, location, and employer.

What skills and qualifications are needed to thrive as a verification and validation engineer?

To thrive as a Verification and Validation Engineer, you need a solid background in engineering principles, software or hardware testing methodologies, and a relevant degree such as in electrical, computer, or systems engineering. Familiarity with test automation tools (e.g., Selenium, Jenkins), scripting languages, and standards like ISO or IEEE V&V processes is commonly required, along with certifications such as ISTQB. Attention to detail, analytical thinking, and strong communication skills set top performers apart by enabling thorough test coverage and clear reporting. These skills are essential to ensure products meet quality standards, regulatory requirements, and customer expectations before release.

What is the difference between Verification And Validation Engineer vs Quality Assurance Engineer?

AspectVerification And Validation EngineerQuality Assurance Engineer
CredentialsTypically requires engineering degrees, certifications like ISTQB or ASQ CQEOften holds degrees in engineering, quality management, or related fields; certifications like Six Sigma or ISTQB
Work EnvironmentWorks in product development, testing labs, and manufacturing settingsWorks across development, production, and process improvement environments
Industry UsageCommon in electronics, aerospace, automotive, and medical device industriesWidely used in manufacturing, software, and service industries
FocusEnsures products meet specifications through testing and validationEnsures quality processes are followed to prevent defects

While both roles aim to ensure product quality, Verification And Validation Engineers focus on testing and confirming that products meet specifications, whereas Quality Assurance Engineers develop and maintain quality systems and processes to prevent defects. Both roles often collaborate but serve different stages of the product lifecycle.

How does a verification and validation engineer typically interact with development and QA teams during a project?

A Verification and Validation Engineer works closely with both development and QA teams to ensure that products meet specified requirements and function as intended. They often review design documents, develop test plans, and execute test cases in collaboration with developers, providing feedback on potential issues early in the process. Regular communication and coordination with QA are essential to ensure comprehensive test coverage and resolve defects efficiently. This collaborative approach helps maintain product quality and supports a smooth development lifecycle.

What is a verification and validation engineer?

Verification and Validation Engineers are professionals responsible for ensuring that products, systems, or software meet specified requirements and function as intended. They design and execute tests, review documentation, and analyze results to confirm that deliverables are both built correctly (verification) and serve their intended purpose (validation). Their work is crucial in highly regulated industries like aerospace, automotive, and healthcare, where safety and compliance are critical. These engineers collaborate with development teams to identify defects early and help ensure that projects meet quality standards before release.
What are popular job titles related to Verification And Validation Engineer jobs in Oregon? For Verification And Validation Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Verification And Validation Engineer jobs in Oregon look for? The top searched job categories for Verification And Validation Engineer jobs in Oregon are:
What cities in Oregon are hiring for Verification And Validation Engineer jobs? Cities in Oregon with the most Verification And Validation Engineer job openings:
Verification And Validation Engineer jobs near you
Infographic showing various Verification And Validation Engineer job openings in Oregon as of August 2026, with employment types broken down into 87% Full Time, 6% Part Time, 6% Contract, and 1% Nights. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $114,348 per year, or $55 per hour.

Senior ASIC Design Verification Engineer

K2 Space

OR • On-site

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 5 days ago

Job description

The Role 

We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
  • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Participate in ASIC team interviews.
  • Contribute to advancement of DV methodologies and improvements.
  • Engage external IP providers and verification partners when needed. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
  • Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).
  • Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
  • Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).
  • Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++). 

Nice to Have

  • Experience with developing and integrating reference models.
  • Understanding of low power verification.
  • Familiarity with gate-level simulation and analog behavioral models.
  • Involvement in post-silicon validation planning and execution.
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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