Senior Consultant
San Francisco, CA · On-site
Experience with emulator ZeBu, Palladium & Veloce. FPGA Protyping experience with HAPS, Protium & ProFPGA is plus. Ability to put together emulation top level wrapper with DUT/System Level, clocks ...
San Francisco, CA · On-site
Experience with emulator ZeBu, Palladium & Veloce. FPGA Protyping experience with HAPS, Protium & ProFPGA is plus. Ability to put together emulation top level wrapper with DUT/System Level, clocks ...
San Francisco, CA · On-site
Experience with emulator ZeBu, Palladium & Veloce. FPGA Protyping experience with HAPS, Protium & ProFPGA is plus. Ability to put together emulation top level wrapper with DUT/System Level, clocks ...
Build complex Subsystem emulation models, including design integration, environment setup, compilation, and debug across industry leading platforms (e.g., Veloce, ZeBu, Palladium). * Drive emulation ...
Build complex Subsystem emulation models, including design integration, environment setup, compilation, and debug across industry leading platforms (e.g., Veloce, ZeBu, Palladium). * Drive emulation ...
... Veloce) through silicon failure analysis and debug A day in the life - Developing comprehensive validation strategies and detailed test plans covering functional, performance, power, and stress ...
... Veloce) through silicon failure analysis and debug A day in the life - Developing comprehensive validation strategies and detailed test plans covering functional, performance, power, and stress ...
Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, SynopsysZeBu, Mentor Veloce) for system-level verification and performance validation. * Collaborate with design ...
Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, SynopsysZeBu, Mentor Veloce) for system-level verification and performance validation. * Collaborate with design ...
Santa Clara, CA · On-site
$144K - $199K/yr
Hands-on experience with Synopsys ProtoCompiler or Synplify Premier, Xilinx Vivado, and familiarity with emulation platforms such as Synopsys ZeBu or Siemens Veloce. * Exposure to ASIC design and ...
Santa Clara, CA · On-site
$144K - $199K/yr
Hands-on experience with Synopsys ProtoCompiler or Synplify Premier, Xilinx Vivado, and familiarity with emulation platforms such as Synopsys ZeBu or Siemens Veloce. * Exposure to ASIC design and ...
$170K - $250K/yr
Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on platforms such as Palladium, ZeBu, or Veloce. * Define and evolve emulation strategy, methodology, and ...
Quick apply
$170K - $250K/yr
Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on platforms such as Palladium, ZeBu, or Veloce. * Define and evolve emulation strategy, methodology, and ...
... Veloce) through silicon failure analysis and debug A day in the life - Developing comprehensive validation strategies and detailed test plans covering functional, performance, power, and stress ...
... Veloce) through silicon failure analysis and debug A day in the life - Developing comprehensive validation strategies and detailed test plans covering functional, performance, power, and stress ...
What You Can Expect - Lead the development of complex SoC emulation models , including design integration, environment setup, compilation, and debug across industryleading platforms (e.g., Veloce ...
What You Can Expect - Lead the development of complex SoC emulation models , including design integration, environment setup, compilation, and debug across industryleading platforms (e.g., Veloce ...
Sunnyvale, CA · On-site
$159K - $194K/yr
Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, Synopsys ZeBu, Mentor Veloce) for system-level verification and performance validation. * Collaborate with design ...
Sunnyvale, CA · On-site
$159K - $194K/yr
Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, Synopsys ZeBu, Mentor Veloce) for system-level verification and performance validation. * Collaborate with design ...
Synthesize the Verilog RTL and create models and compile them to emulators like Veloce/Palladium/Zebu and/or FPGA platforms * Develop all aspects of hardware emulator implementation, with emphasis on ...
Synthesize the Verilog RTL and create models and compile them to emulators like Veloce/Palladium/Zebu and/or FPGA platforms * Develop all aspects of hardware emulator implementation, with emphasis on ...
... Veloce) through silicon failure analysis and debug A day in the life - Developing comprehensive validation strategies and detailed test plans covering functional, performance, power, and stress ...
... Veloce) through silicon failure analysis and debug A day in the life - Developing comprehensive validation strategies and detailed test plans covering functional, performance, power, and stress ...
Los Angeles, CA · On-site
$170K - $250K/yr
Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on platforms such as Palladium, ZeBu, or Veloce. * Define and evolve emulation strategy, methodology, and ...
Quick apply
Los Angeles, CA · On-site
$170K - $250K/yr
Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on platforms such as Palladium, ZeBu, or Veloce. * Define and evolve emulation strategy, methodology, and ...
What You Can Expect Build complex Subsystem emulation models, including design integration, environment setup, compilation, and debug across industry-leading platforms (e.g., Veloce, ZeBu, Palladium ...
What You Can Expect Build complex Subsystem emulation models, including design integration, environment setup, compilation, and debug across industry-leading platforms (e.g., Veloce, ZeBu, Palladium ...
Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, SynopsysZeBu, Mentor Veloce) for system-level verification and performance validation. * Collaborate with design ...
Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, SynopsysZeBu, Mentor Veloce) for system-level verification and performance validation. * Collaborate with design ...
Tucson, AZ · On-site
$122K - $157K/yr
Experience with emulation platforms such as Veloce. * Strong technical documentation and review support experience. #cj
Tucson, AZ · On-site
$122K - $157K/yr
Experience with emulation platforms such as Veloce. * Strong technical documentation and review support experience. #cj
Santa Clara, CA · On-site
$159K - $195K/yr
Hands-on experience with emulation platforms such as Synopsys ZeBu, Siemens Veloce Synopsys or Cadence Z3. Familiarity with ProtoCompiler or Synplify Premier, Xilinx Vivado, * Extensive knowledge of ...
Santa Clara, CA · On-site
$159K - $195K/yr
Hands-on experience with emulation platforms such as Synopsys ZeBu, Siemens Veloce Synopsys or Cadence Z3. Familiarity with ProtoCompiler or Synplify Premier, Xilinx Vivado, * Extensive knowledge of ...
Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, SynopsysZeBu, Mentor Veloce) for system-level verification and performance validation. * Collaborate with design ...
Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, SynopsysZeBu, Mentor Veloce) for system-level verification and performance validation. * Collaborate with design ...
Tucson, AZ · On-site
$116K - $149K/yr
... Veloce
Tucson, AZ · On-site
$116K - $149K/yr
... Veloce
Tucson, AZ · On-site
$111K - $143K/yr
Experience with emulation platforms such as Veloce. * Strong technical documentation and review support experience. #cj
Tucson, AZ · On-site
$111K - $143K/yr
Experience with emulation platforms such as Veloce. * Strong technical documentation and review support experience. #cj
San Jose, CA · On-site
$186K - $267K/yr
Prior emulation experience on platforms such as Palladium, Veloce, or Zebu as well as experience with compilation and debug. * Prior experience with Verilog and System Verilog. * Prior experience ...
San Jose, CA · On-site
$186K - $267K/yr
Prior emulation experience on platforms such as Palladium, Veloce, or Zebu as well as experience with compilation and debug. * Prior experience with Verilog and System Verilog. * Prior experience ...
$8.89 - $13.70
16% of jobs
$15.17 is the 25th percentile. Wages below this are outliers.
$13.70 - $18.51
29% of jobs
The median wage is $19.71 / hr.
$18.51 - $23.32
19% of jobs
$27.58 is the 75th percentile. Wages above this are outliers.
$23.32 - $28.13
12% of jobs
$28.13 - $32.93
8% of jobs
$32.93 - $37.74
5% of jobs
$37.74 - $42.55
4% of jobs
$42.55 - $47.36
2% of jobs
$47.36 - $52.16
2% of jobs
$52.16 - $56.97
1% of jobs
$56.97 - $61.78
1% of jobs
$8
$26
$61
| Aspect | Veloce | Data Analyst |
|---|---|---|
| Required Credentials | Technical certifications, programming skills | Degree in statistics, data science, or related field |
| Work Environment | Tech companies, automotive, or manufacturing sectors | Business, finance, healthcare, or tech industries |
| Employer & Industry Usage | Used in industries focusing on automation, robotics, or automotive | Common in organizations analyzing data to inform decisions |
| Search & Comparison Intent | Often compared for technical roles involving automation | Compared for data analysis and reporting roles |
Veloce typically refers to roles involving automation, robotics, or automotive technology, requiring technical skills and certifications. Data Analysts focus on interpreting data to support business decisions, often with a background in statistics or data science. While both roles may involve technical skills, Veloce is more aligned with engineering and automation sectors, whereas Data Analysts are prevalent across various industries analyzing data for strategic insights.

Emulation Expert: Consulting & Turnkey projects Virtusa Semiconductor BU is looking for seasoned professionals in the Hardware Assisted Verification domain. . Virtusa is invested in AI/HPC [High Performance Computing] customers who are emphasizing on shift left pre-silicon approaches. Designs are getting large in terms of ASIC gates [4B to 20+ BG] with complex System Level Environment targeting latest protocol interfaces for scale up and scale out data centers Virtusa is looking for experts who can set up the emulation environment from scratch to manage the existing environment with design porting to demonstrating a first pass functional environment. Job Description Application or Product Engineering background with minimum 5 to 20 years of experience is required in HW Assisted Verification. Knowledge of FW/SW/Driver with Linux Boot bring up experience is an essential requirement. Knowledge of PCIe, HBM and JTAG/UART protocols is must.. ENET protocol & testers like Virtual IXIA is plus. Skills Requirements Digital design with systeme verilog RTL coding from Synthesis point of view.. Experience with emulator ZeBu, Palladium & Veloce. FPGA Protyping experience with HAPS, Protium & ProFPGA is plus. Ability to put together emulation top level wrapper with DUT/System Level, clocks/reset & FPGA partitioning/Place & Route timing closure for successful model build. Knowledge of Python, C/Perl scripting is a must. Expertise in HW assisted Verification TestBench environment : UVM, C++/System C is desired. Experience integrating and bringing up PCIe Gen6 Protocol Transactor Integration with QeMu is required. Kernel boot, Linux Boot sequences knowledge & debug is must.
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