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Validation Debug Engineer Pcie Jobs (NOW HIRING)

Advanced Micro Devices

$88K - $116K/yr

Providing validation and debug recommendations to customers for validation, new features and debug ... PCIe/CXL functional and protocol (e.g. Gen1~Gen6) debug, including PCIe/CXL IP bring up, validation ...

Advanced Micro Devices

Gen1~Gen6) debug, including PCIe/CXL IP bring up, validation and analysis. * DDR Memory functional ... Programming/scripting skills (e.g. Python, C++, Perl, Ruby etc). * Debug techniques and ...

Socket.dev

Lead Systems Debug Engineer

Bellevue, WA · On-site

Gen1~Gen6) debug, including PCIe/CXL IP bring up, validation and analysis. * DDR Memory functional ... Programming/scripting skills (e.g. Python, C++, Perl, Ruby etc). * Debug techniques and ...

Graphcore

Principal System Debug Engineer

Austin, TX · On-site

Lead System Debug Engineer - Server & Rack Validation (Principal Level and Above)Position Overview ... Deep understanding of industry-standard server interconnects and software stacks, including PCIe ...

TEKsystems

Validation Engineer

Roseville, CA · On-site

$65 - $100/hr

A validation engineer develops a comprehensive test plan by utilizing design specifications ... debugging and problem-solving complex SOC is a must as well. Protocols knowledge PCIe or SAS/SATA ...

TEKsystems

Validation Engineer

Roseville, CA

A validation engineer develops a comprehensive test plan by utilizing design specifications ... debugging and problem-solving complex SOC is a must as well. Protocols knowledge PCIe or SAS/SATA ...

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How much do validation debug engineer pcie jobs pay per hour?

As of Sep 11, 2026, the average hourly pay for validation debug engineer pcie in the United States is $52.00, according to ZipRecruiter salary data. Most workers in this role earn between $39.42 and $63.22 per hour, depending on experience, location, and employer.

What is the difference between Validation Debug Engineer Pcie vs Validation Engineer?

AspectValidation Debug Engineer PcieValidation Engineer
CertificationsRelevant certifications like ISTQB, hardware validation coursesSimilar certifications, often including ISTQB or industry-specific courses
Work EnvironmentHardware labs, embedded systems, PCIe testing setupsSystem testing, software validation, hardware-software integration
Industry UsageSemiconductor, hardware manufacturing, PCIe technologyElectronics, software, hardware validation across industries

Validation Debug Engineer Pcie focuses on testing and debugging PCIe hardware interfaces, requiring specialized knowledge of PCIe protocols and hardware testing. Validation Engineer has a broader scope, covering various hardware and software validation tasks across different technologies. Both roles require similar certifications and work environments but differ in their specific technical focus and industry applications.

Are validation debug engineers in demand?

Validation debug engineers, especially those working with PCIe and other high-speed interfaces, are in demand due to the increasing complexity of hardware and the need for thorough testing and debugging. Skills in hardware validation, debugging tools, and scripting are highly valued in industries such as semiconductor and electronics manufacturing. The demand is driven by ongoing advancements in technology and the need for reliable, high-performance systems.

Do validation debug engineers Pcie make good money?

Validation Debug Engineers specializing in PCIe typically earn competitive salaries that vary by experience, location, and industry. Entry-level positions may start around $70,000 annually, while experienced engineers can earn over $120,000, especially with skills in debugging tools and hardware design. Certifications and working in high-demand tech regions can further increase earning potential.

What are popular job titles related to Validation Debug Engineer Pcie jobs?

For Validation Debug Engineer Pcie jobs, the most frequently searched job titles are:

Infographic showing various Validation Debug Engineer Pcie job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 87% Full Time, 9% Part Time, and 3% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $108,152 per year, or $52 per hour.

PCIe Silicon Validation & Debug Engineer (x2)

Sunnyvale, CA • On-site

Judge Group, Inc.
Recruiting and Staffing Services • 5 - 10K employees
Learn more about Judge Group, Inc.external

$60 - $65/hr

Other

Medical, Dental, Vision

Posted 10 days ago

Key responsibilities

  • Develop and execute test plans for PCIe IP blocks and SoC-level integration in both pre-silicon and post-silicon environments.

  • Debug PCIe link training, protocol, and silicon-level issues using protocol analyzers, oscilloscopes, and logic analyzers.

  • Collaborate with design, platform, firmware, and BIOS teams to validate PCIe functionality, performance, and compliance.

Job description

Location: Sunnyvale, CA Salary: $60.00 USD Hourly - $65.00 USD Hourly Description: Our client is currently seeking a PCIe Silicon Validation & Debug Engineer (x2)
OVERVIEW
  • Looking for engineers with hands-on PCIe validation, debug, and silicon bring-up experience, ideally supporting PCIe Gen4, Gen5, or Gen6 environments.
  • Must have experience in pre-silicon and/or post-silicon validation, including link training, protocol analysis, root cause investigation, and hardware debugging.
  • Strong understanding of PCIe architecture, LTSSM, transaction layers, data link layers, equalization, power management, and compliance testing.
  • Candidates should be comfortable working in both lab environments and silicon validation environments, utilizing protocol analyzers, oscilloscopes, logic analyzers, FPGA platforms, or emulation systems.
  • Experience with SystemVerilog/UVM, test development, automation, and scripting (Python preferred) is highly desirable.
  • Strong target backgrounds include AMD, Nvidia, Intel, Broadcom, Marvell, Astera Labs, Cisco Silicon One, Qualcomm, Google, Meta, and other semiconductor or high-performance compute organizations.
  • This is a true silicon validation and debug role, not a software QA, test automation, or generic verification position.
  • Candidates with a blend of PCIe validation, ASIC/SoC validation, FPGA validation, board bring-up, and hardware debug experience are likely to be the strongest fits.

____________________________________________________________________________________
JOB DESCRIPTION
Summary
We are seeking a skilled PCIe Engineer to join our Silicon Engineering team. The ideal candidate will have deep expertise in PCI Express (PCIe) interfaces and protocols, with hands-on experience in test development, analysis, and debug across both pre-silicon and post-silicon environments. You will play a critical role in ensuring the functional correctness, performance, and compliance of PCIe IP and SoC-level interconnects.
Key Responsibilities
Pre-Silicon
  1. Develop and execute test plans for PCIe Gen3/Gen4/Gen5/Gen6 IP blocks and SoC-level integration
  2. Create directed and constrained-random tests targeting PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and Physical Layer (PHY) functionality
  3. Perform protocol-level analysis using VIP (Verification IP) environments and bus functional models
  4. Debug RTL-level issues related to link training, power management (ASPM, L-states), equalization, and error handling
  5. Collaborate with design teams on coverage closure, assertions, and functional coverage models

Post-Silicon
  1. Bring up and validate PCIe links on silicon platforms (FPGA, emulation, and first silicon)
  2. Develop and execute post-silicon validation test plans covering link training, enumeration, data integrity, error injection, and compliance
  3. Debug silicon-level issues using protocol analyzers (e.g., Keysight, Teledyne LeCroy), oscilloscopes, and logic analyzers
  4. Perform root-cause analysis of PCIe link failures, packet errors, and performance degradation
  5. Characterize PCIe PHY performance including jitter, eye diagrams, and signal integrity
  6. Collaborate with platform, firmware, and BIOS teams to resolve system-level PCIe issues
  7. Drive compliance and interoperability testing per PCI-SIG specifications

General
  1. Analyze PCIe specification updates and assess impact on existing IP/SOC designs
  2. Automate test infrastructure, result parsing, and regression frameworks
  3. Document findings, debug methodologies, and test coverage metrics
  4. Contribute to team knowledge sharing

Required Qualifications
  1. Education: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field
  2. Experience: 3-8+ years of experience in PCIe validation, verification, or silicon bring-up
  3. Strong understanding of PCIe specification (Gen3 through Gen5/Gen6), including:
  4. Transaction Layer: TLP types, ordering rules, flow control, completion handling
  5. Data Link Layer: ACK/NAK, replay, LCRC, DLLP
  6. Physical Layer: Link training (LTSSM), equalization, encoding (8b/10b, 128b/130b)
  7. Power management: ASPM, L-states, D-states
  8. Proficiency in System Verilog/UVM for pre-silicon test development
  9. Experience with protocol analyzers and lab debug tools for post-silicon validation
  10. Familiarity with scripting languages (Python, Perl, Tcl) for test automation and log parsing
  11. Solid understanding of PCIe enumeration, BAR programming, and configuration space
  12. Experience with FPGA prototyping or emulation platforms is a plus

Preferred Qualifications
  1. Experience with CXL (Compute Express Link) or other PCIe-based protocols
  2. Knowledge of signal integrity concepts (S-parameters, eye diagrams, jitter analysis)
  3. Familiarity with compliance testing per PCI-SIG specifications and test suites
  4. Experience with NVMe, CCIX, or UCIe protocols
  5. Background in SoC-level integration and system-level validation
  6. Understanding of BIOS/firmware interactions with PCIe subsystems
  7. Contributions to PCIe IP development or architecture definition

Medical, dental, and vision insurance are available to qualified candidates who meet eligibility requirements.
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