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Telecommute Asic Rtl Design Engineer Jobs in New Jersey

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ ยท On-site

$141K/yr

... ASIC and FPGA designs. You will work closely with design and development teams to ensure compliance with specifications and industry standards. Key Responsibilities * Develop and implement UVM-based ...

FPGA Engineer

Moorestown, NJ ยท On-site

$128K - $164K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

JAva big data engineer

Jersey City, NJ ยท On-site

$54.75 - $70.75/hr

Restful design (Restful in nature) * Model driven development * AST (Generating & Sharing) * Model ... Parse & Compile JSP, Spark B Qualifications asic Criteria * Candidates who had worked in reputed ...

JAva big data engineer

Jersey City, NJ ยท On-site

$54.75 - $70.75/hr

Restful design (Restful in nature) * Model driven development * AST (Generating & Sharing) * Model ... Parse & Compile JSP, Spark B Qualifications asic Criteria * Candidates who had worked in reputed ...

Be Seen First

Telecommuting: Hybrid Position Summary We are seeking a highly motivated and experienced Systems Engineer to lead the design, integration, and deployment of complex rack-mounted systems utilizing ...

#14 - SOFTWARE DEVELOPER

Cherry Hill, NJ ยท On-site

$80 - $120/hr

Design, code, test, implement and support core application components and makes recommendations ... Relocation/ telecommuting may be required plus travel to various unanticipated client locations ...

Lead Infrastructure Engineer

Jersey City, NJ ยท On-site

$117K - $154K/yr

Develop and design the architecture for electronic trading systems, ensuring scalability ... Network system architecture (processor, ASIC, FPGA, port capabilities, packet forwarding, buffers ...

Lead Infrastructure Engineer

Jersey City, NJ ยท On-site

$112K - $147K/yr

Develop and design the architecture for electronic trading systems, ensuring scalability ... Network system architecture (processor, ASIC, FPGA, port capabilities, packet forwarding, buffers ...

No telecommuting or remote work. Note: Looking for candidates who can work on our payroll ... Able to do analysis, design, coding and testing and work as a individual contributor. Additional ...

NJ ยท On-site

$160.80 - $175/hr

Job Title Axiom Developer, AVP Overview Design, develop, and improve software using engineering ... Work in a hybrid environment, with occasional telecommuting as permitted. Leadership & Behavioral ...

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Showing results 41-60

Telecommute Asic Rtl Design Engineer information

What are some common challenges faced by telecommute ASIC RTL design engineers, and how can they be addressed?

Telecommute ASIC RTL Design Engineers often face challenges like coordinating effectively with remote teams, ensuring version control integrity, and maintaining clear communication on project specifications. These challenges can be mitigated by utilizing robust collaboration tools, adhering to standardized documentation practices, and scheduling regular virtual meetings for design reviews. Additionally, staying proactive in seeking feedback and clarifying requirements helps ensure alignment and prevents costly design iterations.

What are the key skills and qualifications needed to thrive as a telecommute ASIC RTL design engineer?

To thrive as a Telecommute ASIC RTL Design Engineer, you need a strong background in digital logic design, proficiency in hardware description languages like Verilog or VHDL, and typically a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, as well as experience with simulation, synthesis, and debugging environments, is essential. Strong problem-solving abilities, attention to detail, and effective communication skills are crucial for collaborating remotely and ensuring design accuracy. These skills are vital to deliver complex, high-performance ASICs on schedule while working efficiently in a remote setting.

What is a telecommute ASIC RTL design engineer?

A Telecommute ASIC RTL Design Engineer is a professional who specializes in designing digital circuits at the Register Transfer Level (RTL) for Application-Specific Integrated Circuits (ASICs), while working remotely. They use hardware description languages like Verilog or VHDL to create and verify circuit designs tailored to specific applications. Their responsibilities often include developing, simulating, and optimizing digital logic, collaborating with cross-functional teams, and ensuring that the final silicon meets design specifications. Since the role is telecommute, all work is performed from a remote location using digital communication and collaboration tools.

What is the difference between Telecommute Asic Rtl Design Engineer vs Telecommute Digital IC Design Engineer?

AspectTelecommute Asic Rtl Design EngineerTelecommute Digital IC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering or Computer Engineering; experience with RTL codingBachelor's or Master's in Electrical Engineering or Computer Engineering; experience with digital circuit design
Work EnvironmentRemote, primarily designing RTL code for ASICsRemote, focusing on digital IC architecture and design
Industry UsageCommon in semiconductor and electronics companies

Both roles often require similar educational backgrounds and work remotely in the semiconductor industry. The main difference lies in their focus: RTL Design Engineers concentrate on writing RTL code for ASICs, while Digital IC Design Engineers work on broader digital circuit architecture. Candidates should choose based on their specific skills and career interests in digital design or RTL coding.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in New Jersey? The most popular types of Asic Rtl Design Engineer jobs in New Jersey are:
What cities in New Jersey are hiring for Telecommute Asic Rtl Design Engineer jobs? Cities in New Jersey with the most Telecommute Asic Rtl Design Engineer job openings:

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Airspan

Warren, NJ โ€ข On-site

$141K/yr

Full-time

Re-posted 3 days ago


Job description

Airspan Careers
UVM SYSTEMVERILOG VERIFICATION ENGINEER
Location: Warren, New Jersey, Plano, TX or REMOTE U.S.
Company: AirSpan Networks
About AirSpan
AirSpan Networks is a global provider of innovative 4G and 5G network solutions, enabling efficient and cost-effective connectivity for operators, enterprises, and industrial applications. We are looking for a skilled UVM SystemVerilog Verification Engineer to join our dynamic team and contribute to the validation and testing of our cutting-edge communication technologies.
Job Description
As a UVM Verification Engineer, you will be responsible for developing and executing test plans using Universal Verification Methodology (UVM) to validate the functionality, performance, and reliability of AirSpan's ASIC and FPGA designs. You will work closely with design and development teams to ensure compliance with specifications and industry standards.
Key Responsibilities
  • Develop and implement UVM-based verification plans and test strategies for FPGA designs.
  • Perform functional, system-level, and regression testing for digital hardware components.
  • Create test benches, test cases, and automation frameworks in System Verilog.
  • Analyze test results, debug issues, and collaborate with design teams to resolve defects.
  • Ensure compliance with industry standards and customer requirements.
  • Provide documentation and reports on test procedures, results, and defect tracking.
  • Continuously optimize test processes and tools to improve efficiency and accuracy.

Qualifications & Experience
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
  • 10 years of experience in UVM-based verification of FPGA systems.
  • Strong understanding of SystemVerilog and Universal Verification Methodology (UVM).
  • Proficiency in scripting languages such as Python or Perl for automation.
  • Experience with simulation tools such as ModelSim or QuestaSim.
  • Experience with C/C++
  • Experience in implementing Bit Accurate Models and debugging DSP designs
  • Familiarity with debugging tools, coverage metrics, and formal verification techniques.
  • Strong problem-solving and analytical skills with attention to detail.
  • Knowledge of O-RAN architecture and protocols for 4G and 5G networks.
  • Ability to work collaboratively in a fast-paced, cross-functional team environment.
  • Design experience a plus.

Preferred Skills
  • Experience in verification of communication protocols.
  • Knowledge of FPGA development and hardware description languages such as VHDL/Verilog.
  • Understanding of hardware/software co-verification techniques.