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Tapeout Manager Jobs (NOW HIRING)

Ownership of full-cycle CPU program management-from spec to tapeout and post-silicon debug. * Ability to define scope, schedule, and resources, and lead execution across architecture, design ...

Senior Staff Engineer, Foundry

San Diego, CA · On-site

$58.75 - $75.75/hr

Manage and drive major fundamental changes to frame and reticle tapeout structures and procedures to accommodate changing assembly and customer product performance needs * Lead end-to-end foundry ...

Lead or guide tapeout readiness activities, including final signoff checks, waiver management, antenna-related issue resolution, deliverable preparation, and coordination of critical verification ...

Senior Staff Engineer, Foundry

San Diego, CA · On-site

$58.75 - $75.75/hr

Manage and drive major fundamental changes to frame and reticle tapeout structures and procedures to accommodate changing assembly and customer product performance needs * Lead end-to-end foundry ...

Lead or guide tapeout readiness activities, including final signoff checks, waiver management, antenna-related issue resolution, deliverable preparation, and coordination of critical verification ...

Lead or guide tapeout readiness activities, including final signoff checks, waiver management, antenna-related issue resolution, deliverable preparation, and coordination of critical verification ...

Manage tapeout activities, ensuring sign‑off for DRC, LVS, timing, power integrity, and reliability. * Collaborate with RTL, architecture, and verification teams to influence design decisions for ...

... tapeout flows. You have worked directly with multi-die and package layout tools, and SI/PI, thermal ... This Technical Product Management role requires substantial engineering depth. Success depends on ...

$40.75 - $52.50/hr

The team partners closely with Technology Development, Mask Technology Center (MTC), OPC, tapeout ... Hiring managers may view your performance appraisals, original resume, transcripts or other ...

Showing results 21-40

Tapeout Manager information

What is the difference between Tapeout Manager vs Design Engineer?

AspectTapeout ManagerDesign Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering or related field; experience in chip design and tapeout processesBachelor's or Master's in Electrical Engineering, Computer Engineering, or related field; strong design and simulation skills
Work EnvironmentCollaborative, project management-focused, often in semiconductor or electronics companiesDesign-focused, technical, often in R&D or design teams within semiconductor companies
Industry UsageCommonly used in semiconductor manufacturing and ASIC/IP development companiesWidely used in chip design, electronics, and integrated circuit development firms

The main difference is that a Tapeout Manager oversees the entire tapeout process, coordinating teams and schedules, while a Design Engineer focuses on creating and simulating circuit designs. Both roles require technical expertise, but the Tapeout Manager emphasizes project management and process coordination, whereas the Design Engineer emphasizes technical design skills.

What are popular job titles related to Tapeout Manager jobs?

For Tapeout Manager jobs, the most frequently searched job titles are:

Infographic showing various Tapeout Manager job openings in the United States as of September 2026, with employment types broken down into 87% Full Time, 12% Part Time, and 1% Contract. Highlights an 79% Physical, 2% Hybrid, and 19% Remote job distribution.

Senior Engineering Program Manager

Santa Clara, CA • On-site

$200K - $500K/yr

Other

Medical, Dental, Vision, PTO

Posted 26 days ago


Job description

Role Overview

Velaura is designing the compute silicon that will power the next generation of robots, autonomous systems, and intelligent machines operating in the physical world. As Senior Engineering Program Manager, you will drive execution of our Physical AI System-on-Chip (SoC) program across its full scope: silicon development, platform hardware, software, and third-party IP (3PIP) vendors.

This role is the connective tissue of the program. You will own the integrated program schedule from architecture through tapeout, silicon bring-up, and platform/software readiness— coordinating internal engineering teams, external IP providers, and manufacturing partners. You will surface risks early, drive decisions to closure, and keep a complex, multi-disciplinary program moving at startup speed.

Responsibilities
  • Own the end-to-end SoC program plan: define and maintain the integrated schedule spanning architecture, RTL design, verification, physical design, tapeout, silicon bring-up, and production readiness.
  • Drive platform and software program execution in parallel with silicon—board development, firmware, drivers, SDK, and system validation—so that software and platform readiness track silicon milestones.
  • Manage third‑party IP (3PIP) vendor engagements: track licensing and contract milestones, deliverable schedules, quality metrics, errata, and integration dependencies across multiple IP providers.
  • Run program-level rhythm: milestone reviews, cross‑functional syncs, executive status reporting, and decision logs that keep stakeholders aligned and accountable.
  • Identify, quantify, and drive mitigation of program risks across silicon, platform, software, and vendor workstreams; accelerate with data and proposed options, not just problems.
  • Coordinate external execution partners—foundry, OSAT, design services, and platform manufacturing—on schedules, deliverables, and dependencies.
  • Build the program management processes, tools, and templates for a growing engineering organization, and mentor teams on execution discipline
Required Qualifications
  • 10+ years of engineering program management experience in semiconductors, with at least one complex SoC program managed from architecture through tapeout and bring-up.
  • Demonstrated experience managing programs that span silicon, platform hardware, and software—understanding the distinct execution rhythms and dependencies of each.
  • Hands‑on experience managing third‑party IP vendors, including deliverable tracking, milestone‑based contracts, and cross‑vendor dependency management.
  • Working technical fluency in SoC development: ability to engage credibly in discussions of RTL milestones, verification coverage, physical design closure, DFT, and software/firmware bring‑up.
  • Expert command of program management fundamentals: schedule development and critical-path analysis, risk management, change control, and stakeholder communication.
  • Proven ability to influence without authority across engineering, vendor, and executive audiences; excellent written and verbal communication skills.
  • Bachelor's degree in Electrical/Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
Preferred Qualifications
  • Experience with programs in advanced process nodes and with foundry/OSAT engagement models.
  • Experience in edge AI, automotive, robotics, or other embedded/safety‑adjacent domains, including familiarity with quality and functional‑safety development processes.
  • Experience at an early‑stage or high‑growth company, building program management practices from the ground up.
  • Master's degree in engineering or business.

$200,000 - $500,000 a year

Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a competitive base salary, performance‑based incentives, and equity participation, allowing team members to share in the company’s long‑term success.

Your base pay will depend on your skills, qualifications, experience, and location.

In addition to compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well‑being and growth of our team.

Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.

Why Velaura?

Velaura is building next‑generation compute technology for cloud, edge, and PhysicalAI. Our solutions will enable robots, autonomous systems, drones, and other intelligentmachines to operate efficiently in the physical world.This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry‑defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape thefuture of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity.Qualified applicants will receive consideration for employment without regard to race,color, religion, national origin, gender, sexual orientation, gender identity, disability orprotected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mentaldisabilities. Applicants who would like to contact us regarding the accessibility of ourwebsite or who need special assistance or a reasonable accommodation for any part ofthe application or hiring process may contact us at: careers@velaura.ai. This contact information is for accommodation requests only. Evaluation of requests for reasonableaccommodation will be determined on a case‑by‑case basis.

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