ZipRecruiter

Log In

1

Tapeout Engineering Jobs (NOW HIRING)

Normal Computing

Hardware Engineer, RTL

New York, NY · On-site

$200K - $400K/yr

You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design ...

Analog Devices

Principal EDA Engineer

Wilmington, MA · On-site

Lead or guide tapeout readiness activities, including final signoff checks, waiver management ... MS in Electrical Engineering, Computer Engineering, or a related field, or an equivalent ...

SolGenie

ASIC Physical Design Engineer

Lafayette, IN · On-site

$130K - $134K/yr

Tapeout , Signoff , DRC/LVS/PEX, Customer interaction Job Responsibilities: * Act as the primary ... Collaborate with internal design, layout, and engineering teams to ensure manufacturability

Ralliant

ASIC Physical Design Engineer

Boulder, CO · On-site

$141K - $145K/yr

Our inclusive engineering culture is hardworking, inquisitive, and always eager to learn and grow ... closed, manufacturable, tapeout-ready design. • Develop and maintain scripts, flows ...

EnCharge AI

Staff Physical Design Engineer

$170K - $240K/yr

... tapeout execution. Qualifications and Requirements * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. * 10-15 years of dedicated experience in ...

Tenstorrent

Engineering Program Manager, RISCV

Austin, TX · On-site

$100K - $500K/yr

Ownership of full-cycle CPU program management-from spec to tapeout and post-silicon debug ... Partnering with top engineers to resolve real-time design challenges, drive schedule trade-offs ...

previous page

Showing results 41-60

All JobsManufacturing JobsProduct Manufacturing JobsIndustrial Engineering JobsTapeout Engineering Jobs

Tapeout Engineering information

See salary details

$12

$31

$57

How much do tapeout engineering jobs pay per hour?

As of Sep 13, 2026, the average hourly pay for tapeout engineering in the United States is $31.55, according to ZipRecruiter salary data. Most workers in this role earn between $20.19 and $37.98 per hour, depending on experience, location, and employer.

What is tapeout engineering?

Tapeout engineering refers to the final stage in the semiconductor design process, where the completed integrated circuit (IC) design is sent to manufacturing for fabrication. Tapeout engineers are responsible for ensuring that the design data is error-free, meets all manufacturing requirements, and is ready for photolithography. This process involves close collaboration with design, verification, and fabrication teams to resolve any last-minute issues and ensure a successful chip production. Tapeout is a critical step because any mistakes can be costly and delay product launches.

What are the key skills and qualifications needed to thrive as a tapeout engineer, and why are they important?

To thrive as a Tapeout Engineer, you need a solid background in electrical engineering, semiconductor manufacturing processes, and experience with integrated circuit (IC) design, often supported by a relevant degree. Familiarity with EDA tools such as Cadence or Synopsys, as well as knowledge of design rule checks (DRC) and layout-versus-schematic (LVS) verification, is essential. Strong attention to detail, problem-solving skills, and effective communication are valuable soft skills for coordinating with design and fabrication teams. These competencies ensure the accurate transfer of designs to silicon, minimizing costly errors and enabling successful chip production.

What are some typical challenges faced during the tapeout engineering process, and how can they be addressed?

Tapeout engineers often encounter challenges such as last-minute design changes, tight schedules, and coordination among multiple engineering teams. These issues can be addressed by implementing rigorous design verification processes, maintaining clear communication channels with design, layout, and fabrication teams, and utilizing robust project management tools. Staying organized and proactive in monitoring design rule checks and sign-off criteria are essential to ensuring a successful tapeout with minimal delays.

What are popular job titles related to Tapeout Engineering jobs?

For Tapeout Engineering jobs, the most frequently searched job titles are:

Hardware Engineer, RTL

New York, NY • On-site

Normal Computing
See more jobs at Normal Computingexternal

$200K - $400K/yr

Full-time

Re-posted 11 days ago

Key responsibilities

  • Design and verify digital logic at the microarchitecture level, including writing synthesizable SystemVerilog RTL.

  • Collaborate with architecture, verification, and physical design teams to ensure design meets specifications, timing, and area constraints.

  • Support tapeout preparation, integration, and post-silicon bring-up activities.

Job description

Normal Computing | Build with Us
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, San Francisco, London, Copenhagen, and Pangyo.
The Role
As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence.
You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely with physical design to make sure the design meets area and timing constraints. Because Normal's chips are not standard accelerators, the RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it.
This is a role for an engineer who collaborates effectively across teams, including architecture, verification and physical design. The strongest candidates have taped out silicon, written RTL and helped close coverage, and are comfortable working in an environment where the specification is still being developed in parallel.
What You Will Own
  • RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.
  • Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures.
  • Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage.
  • Physical Design Collaboration: Collaborate with physical design on timing closure, floorplanning constraints, and DFT.
  • Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation.
  • Tapeout & Bring-up: Support tapeout preparation, integration, and post-silicon bring-up as needed.
What Makes You a Great Fit
  • Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route
  • Experience in closing coverage to a high level
  • At least one tapeout in your background, from any node and any company size
  • Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
  • Strong debugging instincts across simulation, waveforms, and formal counterexamples
  • Ability to work directly with architects and physical designers without needing a large intermediary layer
  • Industry experience in ASIC or SoC design
Bonus Points
  • Experience at an AI chip company where design and verification were tightly coupled
  • Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6
  • Familiarity with RISC-V or other open ISAs
  • Experience with AI-assisted RTL or EDA tooling in your design workflow
  • Exposure to physical design constraints, floorplanning, or timing-driven RTL development

Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

Apply