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Substrate Design Engineer Layout Jobs (NOW HIRING)

Cspeed

Package Design & Layout Engineer

Palo Alto, CA · On-site

Deliver RDL/UBM and package substrate layouts for our optical engine products and test vehicles ... Iterate with SI/PI engineers on test routes to converge routing topologies and design rules. Design ...

Cspeed

Package Design & Layout Engineer

Palo Alto, CA · On-site

Deliver RDL/UBM and package substrate layouts for our optical engine products and test vehicles ... Iterate with SI/PI engineers on test routes to converge routing topologies and design rules. Design ...

Socket.dev

Package Layout Engineer

Mountain View, CA · On-site

$157K - $176K/yr

About This Role Lightmatter is looking for a Package Layout Design Engineer to drive the next ... Generate fab files and coordinate with substrate suppliers and OSATs to support Design for ...

Lightmatter

Package Layout Engineer

Mountain View, CA · On-site

$157K - $176K/yr

About This Role Lightmatter is looking for a Package Layout Design Engineer to drive the next ... Generate fab files and coordinate with substrate suppliers and OSATs to support Design for ...

Intel

ADCE Packaging Design Architect

Hillsboro, OR · On-site

$220K - $311K/yr

... layout and routing of the package design. Performs substrate fit and routing studies to establish ... Self-motivated engineer who has strong technical background in design and electrical analysis.

New

Intel

ADCE Packaging Design Architect

Phoenix, AZ · On-site

$220K - $311K/yr

... layout and routing of the package design. Performs substrate fit and routing studies to establish ... Self-motivated engineer who has strong technical background in design and electrical analysis.

New

Intel

$220K - $311K/yr

... layout and routing of the package design. Performs substrate fit and routing studies to establish ... Self-motivated engineer who has strong technical background in design and electrical analysis.

New

Ciena

Principal SI/PI Design Engineer

New Providence, NJ · On-site

$148K - $237K/yr

Responsible for package/SIP layout, optimization, design verification and tapeout * Interface and ... Substrate design experience for RF, digital, high speed and mixed signal die * Thorough ...

Intel

ADCE Packaging Design Architect

Fort Collins, CO · On-site

$220K - $311K/yr

... layout and routing of the package design. Performs substrate fit and routing studies to establish ... Self-motivated engineer who has strong technical background in design and electrical analysis.

New

Intel

ADCE Packaging Design Architect

Albuquerque, NM · On-site

$220K - $311K/yr

... layout and routing of the package design. Performs substrate fit and routing studies to establish ... Self-motivated engineer who has strong technical background in design and electrical analysis.

New

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Substrate Design Engineer Layout information

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How much do substrate design engineer layout jobs pay per year?

As of Sep 13, 2026, the average yearly pay for substrate design engineer layout in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What does a substrate design engineer layout do?

A Substrate Design Engineer Layout is responsible for designing and developing the physical layout for substrates used in semiconductor devices, such as integrated circuits and printed circuit boards (PCBs). They use specialized software to create layouts that meet electrical, thermal, and mechanical requirements, ensuring optimal performance and manufacturability. Their work involves collaborating with electrical engineers, manufacturing teams, and other stakeholders to translate schematic diagrams into detailed substrate layouts. Additionally, they may be involved in reviewing prototypes, troubleshooting design issues, and implementing improvements to enhance product reliability and efficiency.

What are the key skills and qualifications needed to thrive as a substrate design engineer layout?

To thrive as a Substrate Design Engineer Layout, you need expertise in PCB design, electrical engineering principles, and a relevant degree such as in electrical or electronics engineering. Proficiency with layout design tools like Cadence Allegro, Mentor Graphics, and knowledge of industry standards such as IPC is typically required. Attention to detail, problem-solving, and effective teamwork are crucial soft skills that set top performers apart. These skills and qualifications are vital for creating reliable, high-performance substrates that meet technical requirements and manufacturing constraints.

What are some typical challenges a substrate design engineer layout might encounter when collaborating with cross-functional teams?

Substrate Design Engineer Layout professionals often work closely with electrical engineers, mechanical engineers, and manufacturing teams to ensure that their designs meet performance, reliability, and manufacturability standards. One common challenge is balancing the technical requirements from different teams, such as signal integrity needs versus manufacturing constraints. Effective communication and proactive problem-solving are essential to address design trade-offs and ensure alignment across the project. Additionally, keeping up with evolving design tools and industry standards can be demanding, but it also provides valuable learning and growth opportunities.

What are popular job titles related to Substrate Design Engineer Layout jobs?

For Substrate Design Engineer Layout jobs, the most frequently searched job titles are:

Infographic showing various Substrate Design Engineer Layout job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 88% Full Time, 8% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $120,849 per year, or $58.1 per hour.

Package Design & Layout Engineer

Palo Alto, CA • On-site

Cspeed
See more jobs at Cspeedexternal

Full-time

Re-posted 10 days ago

Job description

The Role

You will own the physical design of our optical engine packages - redistribution layers, substrate, and the bump and ball maps that tie the die stack to the host board. This is a hands-on layout role with real architectural influence.

You will work between our PIC and EIC design teams, our SI/PI and thermal engineers, and our supply chain (wafer fab, substrate vendor, OSAT). You will not be handed a finished floorplan to route - you will help define it.

What You'll Do

Layout execution

  • Deliver RDL/UBM and package substrate layouts for our optical engine products and test vehicles, from floorplan through tape-out.
  • Define and release bump maps, ball maps, and escape routing strategies for multi-die assemblies (PIC, EIC, and light source die).
  • Design to 200G/lane-class electrical requirements: differential pair routing, reference-plane integrity, crosstalk isolation, and power delivery for high-current, low-noise rails.

Co-design and floor planning

  • Participate from concept phase: produce preliminary floorplans and stack-up proposals that reconcile electrical, optical, thermal, and mechanical constraints before they are frozen.
  • Iterate with SI/PI engineers on test routes to converge routing topologies and design rules.

Design rules, DFM, and supplier engagement

  • Work directly with wafer fabs, substrate suppliers, and OSATs to capture and negotiate design rules, stack-ups, and assembly constraints.
  • Generate fab and assembly release packages; drive DFM/DFA closure and design reviews through to sign-off.
  • Flag rule conflicts early and propose alternatives rather than routing around them silently.

Verification and automation

  • Run and own physical verification: DRC, connectivity/LVS-style netlist checks, and cross-domain consistency between die, package, substrate, and board.
  • Manage netlists for heterogeneous assemblies across revisions and product variants.
  • Build scripted automation (SKILL, Python, or equivalent) for repetitive layout, checking, and release tasks.

Build support

  • Support test vehicle definition, first builds, bring-up, failure analysis, and yield learning - including layout changes driven by assembly reality.
Required Qualifications
  • BS or MS in Electrical Engineering, or equivalent practical background.
  • 6+ years of IC package physical design, including at least one product taken from concept through tape-out and volume-relevant build.
  • Expert-level proficiency in a package layout tool: Cadence Allegro Package Designer / APD+ / SiP, Siemens Xpedition Package Designer, Synopsys IC Package, or equivalent.
  • Demonstrated experience with multi die packaging: 2D or 2.5/3D integration.
  • Working fluency with multi-layer organic substrate construction and how material and stack-up choices constrain routing.
  • Practical experience closing DFM/DFA with external substrate suppliers and OSATs.
  • Comfortable working in English across a distributed team and multiple time zones.
Preferred Qualifications
  • Demonstrated experience with advanced packaging: 2.5D/3D integration, RDL, TSV interposers, fan-out, microbump or Cu-pillar flip-chip.
  • Layout for 112G/224G SerDes or comparable high-speed interfaces; familiarity with signal and power integrity workflows (e.g. Cadence Sigrity/PowerSI, Ansys).
  • Familiarity with mask and RDL vendor flows, GDS-based layout environments (Virtuoso, KLayout), and AutoCAD file exchange.
  • Experience with package/IC co-design environments (e.g. Cadence Integrity 3D-IC).
  • Scripting for design automation and rule checking.
  • Experience at a startup or on a first-of-its-kind product, where the design rules did not exist yet.
Why This Role Is Different

Most package layout roles are a step in someone else's flow. Here, the package is the product. You will be one of a handful of people who determine whether a next-generation optical engine is manufacturable, and you will see your layout decisions land in silicon and in an OSAT line within months, not years.

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