FEA Packaging Engineer
Palo Alto, CA · On-site
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Cspeed
21 Cspeed Jobs Hiring Near You
FEA Packaging Engineer
Palo Alto, CA · On-site
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Thermal Simulation Engineer
Palo Alto, CA · On-site
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Thermal Simulation Engineer
Palo Alto, CA · On-site
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling ...
FEA Packaging Engineer
Palo Alto, CA · On-site
The Role This position performs finite element analysis for CspeedIO optical engine packages across both thermal and structural domains. It is scoped for a strong FEA engineer: demonstrated depth in ...
FEA Packaging Engineer
Palo Alto, CA · On-site
The Role This position performs finite element analysis for CspeedIO optical engine packages across both thermal and structural domains. It is scoped for a strong FEA engineer: demonstrated depth in ...
The Role This position owns test strategy for CspeedIO optical engines, from wafer-level probe through final engine test. The strategy is to be defined rather than inherited. An optical engine is a ...
The Role This position owns test strategy for CspeedIO optical engines, from wafer-level probe through final engine test. The strategy is to be defined rather than inherited. An optical engine is a ...
The Role This position owns structural finite element analysis for CspeedIO optical engine packages: warpage prediction through the assembly process, stress in bump and interconnect structures, and ...
The Role This position owns structural finite element analysis for CspeedIO optical engine packages: warpage prediction through the assembly process, stress in bump and interconnect structures, and ...
At the core of our technology is a high-density III-V laser array - a critical integrated component in our broader optical system - designed for high-volume deployment in AI infrastructure. We are ...
At the core of our technology is a high-density III-V laser array - a critical integrated component in our broader optical system - designed for high-volume deployment in AI infrastructure. We are ...
The Role This position owns thermal modeling for CspeedIO optical engines, from die-level power maps through cooling boundary conditions, and the correlation of those models against measured hardware.
The Role This position owns thermal modeling for CspeedIO optical engines, from die-level power maps through cooling boundary conditions, and the correlation of those models against measured hardware.
The Role You will own the physical design of our optical engine packages - redistribution layers, substrate, and the bump and ball maps that tie the die stack to the host board. This is a hands-on ...
The Role You will own the physical design of our optical engine packages - redistribution layers, substrate, and the bump and ball maps that tie the die stack to the host board. This is a hands-on ...
We are seeking a PCB Design & Validation Engineer to own the design of test/eval boards and lead validation of our high-speed optical transceivers. You will design the PCB platforms that enable ...
We are seeking a PCB Design & Validation Engineer to own the design of test/eval boards and lead validation of our high-speed optical transceivers. You will design the PCB platforms that enable ...
Advanced Packaging Engineer - Fiber Array Integration
Palo Alto, CA · On-site
$151K - $196K/yr
The Role This position owns the detachable optical interface for CspeedIO optical engines: the on-package element, the coupling optics, the alignment features, and the high-volume assembly process ...
Advanced Packaging Engineer - Fiber Array Integration
Palo Alto, CA · On-site
$151K - $196K/yr
The Role This position owns the detachable optical interface for CspeedIO optical engines: the on-package element, the coupling optics, the alignment features, and the high-volume assembly process ...
For more information about C Speed, LLC and additional job opportunities, please visit our website: www.cspeed.com C Speed, LLC provides equal employment opportunities to all employees and applicants ...
For more information about C Speed, LLC and additional job opportunities, please visit our website: www.cspeed.com C Speed, LLC provides equal employment opportunities to all employees and applicants ...
For more information about C Speed, LLC and additional job opportunities, please visit our website: www.cspeed.com C Speed, LLC provides equal employment opportunities to all employees and applicants ...
For more information about C Speed, LLC and additional job opportunities, please visit our website: www.cspeed.com C Speed, LLC provides equal employment opportunities to all employees and applicants ...
For more information about C Speed, LLC and additional job opportunities, please visit our website: www.cspeed.com C Speed, LLC provides equal employment opportunities to all employees and applicants ...
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For more information about C Speed, LLC and additional job opportunities, please visit our website: www.cspeed.com C Speed, LLC provides equal employment opportunities to all employees and applicants ...
For more information about C Speed, LLC and additional job opportunities, please visit our website: www.cspeed.com C Speed, LLC provides equal employment opportunities to all employees and applicants ...
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For more information about C Speed, LLC and additional job opportunities, please visit our website: www.cspeed.com C Speed, LLC provides equal employment opportunities to all employees and applicants ...
Cspeed Jobs Information
Full-time
Posted 7 days ago
Job description
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.
Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true "scale-up" architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.
The Role
This position performs finite element analysis for CspeedIO optical engine packages across both thermal and structural domains. It is scoped for a strong FEA engineer: demonstrated depth in either thermal or mechanical analysis is expected, and the ability to work competently in the other is required.
The analysis supports package architecture decisions and qualification. Temperature governs optical wavelength and channel uniformity. Deformation and interconnect stress govern assembly yield, reliability, and optical coupling, since warpage displaces optical facets. Both sets of results terminate in the same design decisions, which is why the scope is held in one role.
Correlation against measured hardware is a standing expectation. Results are used for design sign-off, so assumptions must be documented and defensible.
Responsibilities
Thermal analysis
Structural analysis
Methodology and correlation
Design and supplier support
This position provides the physics basis for package architecture decisions and qualification.
Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true "scale-up" architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.
The Role
This position performs finite element analysis for CspeedIO optical engine packages across both thermal and structural domains. It is scoped for a strong FEA engineer: demonstrated depth in either thermal or mechanical analysis is expected, and the ability to work competently in the other is required.
The analysis supports package architecture decisions and qualification. Temperature governs optical wavelength and channel uniformity. Deformation and interconnect stress govern assembly yield, reliability, and optical coupling, since warpage displaces optical facets. Both sets of results terminate in the same design decisions, which is why the scope is held in one role.
Correlation against measured hardware is a standing expectation. Results are used for design sign-off, so assumptions must be documented and defensible.
Responsibilities
Thermal analysis
- Build and maintain thermal models spanning die, package, interface materials, lid, and cold plate, and establish cooling boundary conditions and their validity limits.
- Resolve the temperature field across the photonic IC to the resolution photonic design requires, and define the heat extraction path and interface material selection for high-flux die within the assembly.
Structural analysis
- Predict warpage through the assembly process, and own the flatness, coplanarity, and facet planarity budgets that assembly and optical coupling depend on.
- Analyze bump and interconnect stress, chip-package interaction, and fatigue life, supporting qualification against JEDEC or equivalent methodology.
Methodology and correlation
- Define modeling standards and document assumptions such that results are auditable.
- Lead correlation against measured temperature, warpage, cross-section, and reliability data, and revise methodology accordingly.
Design and supplier support
- Provide requirements, constraints, and sign-off criteria during architecture definition rather than after design freeze.
- Engage substrate suppliers, OSATs, and cooling and material vendors on process assumptions and measured data.
- MS or PhD in Mechanical Engineering, Materials Science, Engineering Mechanics, or equivalent practical background.
- 6+ years of finite element analysis for semiconductor packaging or electronic systems, including one product carried from architecture through hardware correlation.
- Expert proficiency in one commercial FEA or CFD tool and working proficiency in a second covering the other domain - for example Ansys Mechanical or Abaqus alongside Icepak, Fluent, Flotherm, or Celsius.
- Sound FEA fundamentals: meshing judgment, boundary condition selection, convergence, and the ability to defend a model rather than only to run one.
- Demonstrated correlation of simulation against physical measurement, and the judgment to distinguish a modeling error from a process excursion.
- Experience with advanced packaging construction: flip chip, 2.5D/3D, interposers, and heterogeneous integration.
- Depth in nonlinear and time-dependent material behavior: creep, viscoplasticity, viscoelasticity, and fatigue.
- Silicon photonics or optoelectronic packaging, including thermo-optic sensitivity or warpage as an optical alignment constraint.
- Coupled thermal-structural workflows, including transfer of a computed temperature field into a structural model.
- Direct-to-chip liquid cooling, or chip-package interaction and low-k dielectric stress.
- Scripting for model automation and parametric studies, and design of experiments methodology.
This position provides the physics basis for package architecture decisions and qualification.