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Sta Static Timing Analysis Engineer Jobs in Texas

CPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

Conducts verification and signoff including formal equivalence verification, static timing analysis ... Bachelors in Computer Engineering or Electrical Engineering or related field with 6+ years of ...

CPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

Conducts verification and signoff including formal equivalence verification, static timing analysis ... Bachelors in Computer Engineering or Electrical Engineering or related field with 2+ years of ...

... timing analysis, and timing closure. Description As a CPU Design Timing Engineer, you will be ... following static timing tools: Primetime or Tempus Experience with cross talk, noise, OCV ...

... timing analysis, and timing closure. Description As a CPU Design Timing Engineer, you will be ... following static timing tools: Primetime or Tempus Experience with cross talk, noise, OCV ...

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner ...

... timing analysis, and timing closure. Description As a CPU Design Timing Engineer, you will be ... following static timing tools: Primetime or Tempus Experience with cross talk, noise, OCV ...

Senior Physical Design Integration Engineer

Austin, TX · On-site

$134K - $138K/yr

The Physical Design Integration Engineer performs physical design implementation of custom CPU ... Conducts verification and signoff including formal equivalence verification, static timing analysis ...

... timing analysis, and timing closure. Description As a CPU Design Timing Engineer, you will be ... following static timing tools: Primetime or Tempus Experience with cross talk, noise, OCV ...

Senior STA Engineer

Austin, TX · On-site

$152.40 - $217.20/hr

Familiarity with clock tree timing analysis and co‑optimization with physical design * Experience ... IR drop analysis (static and dynamic) * Salary range: $152,400 - $217,200 annually. * Employee may ...

New

ASIC Physical Design Engineer

Austin, TX · On-site

$128K - $184K/yr

Conduct static timing analysis (STA) and drive timing closure for multi-mode/multi-corner designs ... Bachelors degree in Engineering + 5 years of related experience, or Masters degree in Engineering ...

... static timing analysis (STA) principles Ability to analyze critical paths and guide RTL designs to optimal solutions Collaborate effectively with IP teams spanning multiple sites Familiarity with DFT ...

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... analysis. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and ...

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... in timing analysis. Minimum Qualifications Bachelors of Science in Electrical Engineering.

Showing results 41-60

Sta Static Timing Analysis Engineer information

What is a STA static timing analysis engineer?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.

What are some common challenges faced by STA static timing analysis engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.
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Infographic showing various Sta Static Timing Analysis Engineer job openings in Texas as of August 2026, with employment types broken down into 86% Full Time, and 14% Part Time. Highlights an 100% In-person job distribution.

CPU Physical Design Engineer

Intel Corporation

Austin, TX • On-site

$134K - $138K/yr

Full-time

Medical, Retirement, PTO

Re-posted 21 days ago


Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 156 rated electronics manufacturers


Job description

Job Details:
Job Description:
Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.
Life at Intel
As a member of Intel's CPU development team, you will have a front seat in designing the latest core IP to power cutting edge compute processors across client, server, IOTG and AI. We innovate state of the art microprocessor architecture on the most advanced and latest process technologies with a focus on power efficiency. Our core designs are present in nearly all segments of Intel's compute roadmap.
Job responsibilities include but are not limited to:
  • Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
  • Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
  • Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
  • Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
  • Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.
  • Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Minimum Qualifications:
  • Bachelors in Computer Engineering or Electrical Engineering or related field with 6+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering or related field (or higher degree) with 4 + years of relevant work experience.
  • 4+ years' experience in Synthesis of a digital logic block or partition.
  • At least 1 Completion of Tape Out on advanced technologies.

4+ years of experience in each of the following:
  • Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure.
  • PV convergence (including static timing and power analysis).
  • Chip physical design verification including formal equivalence, electrical rules, DRC/LVS, and Noise flow.
  • Scripting with TCL.

Preferred Qualifications:
  • 8+ years of Tape Out experience.
  • Strong knowledge with Physical design best known practices concerning floor-planning, routing techniques, clock distribution.
  • Strong knowledge of Static Timing Analysis, Noise analysis, and reliability verification techniques.
  • Strong knowledge of RTL to GDS methodologies and formal equivalence
  • Experience performing CPU level timing analysis and optimization, ensuring designs meet functional and performance requirements.
  • Experience generating and verifying timing constraints while addressing timing violations at the chip or block level for CPU cores.
  • Experience working closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.

Benefits at Intel
Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Texas, Austin
Additional Locations:
Business group:
Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968