Sram Design Engineer Jobs in Portland, OR (NOW HIRING)

Job Description

At the heart of Intel's groundbreaking product advancements, the Logic Technology Development (LTD) organization is a powerhouse of process technology innovation. Our relentless pursuit of excellence and innovation propels Intel's Foundry strategy, ensuring that we not only meet but exceed the aspirations of our global customers. As we continue to lead the semiconductor industry, we are enhancing our technological capabilities to guarantee the triumph of our customers' diverse and ambitious projects.

Your Role in Intel's Foundry Revolution: As a Foundry Technology Development - Staff Yield Engineer, you will be at the forefront of Intel's collaborative journey with our foundry partners. Your expertise will be pivotal in guiding our customers through the intricate journey of product development, starting from testing and validation to New Product Introduction (NPI) phase to the High Volume Manufacturing (HVM). You will play a vital role in overseeing the wafer manufacturing process and ensuring a seamless transition into volume production. This is a unique opportunity to be part of a team that is not just participating in the industry but actively shaping its future.
We are seeking a broad range of semiconductor expertise across the range of foundry technology development.

Based on experience, potential areas may include:

• Serve as the yield point of contact through the cycle of foundry product development, from design to initial High Volume Manufacturing (HVM)
• Define yield goal and roadmap for foundry customer silicon by collaborating with Intel Foundry Services (IFS), Technology Development (TD), and Product Integration
• Collaborate with TD Process Integration, Device, Defect Metro, and Lab to identify yield detractors and yield enhancement opportunities, specifically for foundry customer silicon
• Provide yield / defect density projection for different types of customer silicon, including test chips, shuttles, and products
• Track inline process and non-process changes to incorporate the changepoints into yield prediction model
• Develop yield models to identify potential parametric and defective loss components and support Process Integration, Device and Module teams to develop projects to eliminate systematic yield losses
• Support yield analysis of logic, SRAM, and other types of devices on foundry customer silicon
• Establish correlations between critical inline metrics and yield for better inline control and end of line projection
• Engage side-by-side with Product Integration and Device teams in customer silicon execution, such as skew split planning and DOE
• Lead investigations and root-causing on yield signals for foundry customer silicon
• Identify opportunities to optimize foundry product development operational systems and methodologies to improve efficiency and standardization
• Work as the technical interface between foundry and both internal stakeholders and external customers

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications:

• Bachelor’s Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering or other relevant engineering or physical science discipline with 6+ years of relevant work experience

OR

• Master's Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering or other relevant engineering or physical science with 4+ years of relevant work experience

OR

• PhD Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering or other relevant engineering or physical science discipline with 2+ years of industry experience
   

The years of relevant work experience listed above must be in the field in at least one of the following areas:

• Semiconductor yield engineering
• Analysis of yield post silicon yield signal and root-causing

Preferred Qualifications:

• 3+ years of semiconductor direct yield analysis and engineering experience

• 3+ direct experience in yield pareto, projection and yield roadmap construction
• 3+ years of experience within a foundry team, or foundry customer yield collaboration
• 3+ years of experience interpreting product data including inline, e-test and SORT data, finding failure root cause and inline indicator and driving for solutions
• Knowledge on inline inspection method, electrical test structures and SORT programs
• Exposure to fabless design house product development
• Foundry customer service experience and evidence of strong customer orientation.

For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information

Other Locations
US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in the US $148,100.00-$209,100.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.