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Sip Engineer Jobs in California (NOW HIRING)

Engineering Group, Engineering Group > Packaging Engineering General Summary: Qualcomm Data Center ... Responsible for Package/SIP physical design and layout, optimization, DV, and tape out. * Work with ...

Overview VoIP Engineers are responsible for design, implementation, and maintenance of company ... Manage and maintain company phone numbers (DID, TFN) and SIP trunks with VoIP vendors. * Ensure ...

Video Engineer Location: SFO, CA Duration: 6+ Months BGV will be done for the selected candidates ... Tandberg VCS-C, VCS-E, TMS, MSE, Conductor, MCUs, CTMS, ISDN gateways SIP Troubleshooting ...

IC Package Design Engineer

Los Angeles, CA · On-site

$146K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next-generation package structure and configuration optimization, and own Package/SiP/module physical ...

Principal Packaging Engineer

Irvine, CA · On-site

$129K - $247K/yr

Principal Packaging Engineer Posting Start Date: 3/23/26 Job Location(s): San Jose If you are ... Experience in Advanced RF SiP Moldules: Dual Side BGA, Dual Side Mold Grid Array, EMI Shielding,

We are seeking a Principal Packaging Engineer with expertice in advanced laminate packaging ... Experience in Advanced RF SiP Moldules: Dual Side BGA, Dual Side Mold Grid Array, EMI Shielding,

Familiarity with IP telephony network , SIP, IMS, and IP telephony standards. * Familiarity with air interface performance analysis, characterization and optimization. * Exposure to programming in C ...

Familiarity with IP telephony network , SIP, IMS, and IP telephony standards. * Familiarity with air interface performance analysis, characterization and optimization. * Exposure to programming in C ...

Integrate telephony providers such as Twilio, SIP, or LiveKit Telephony. * Develop scalable backend ... Prompt engineering, tool calling, function calling * RAG, agentic workflows, multi-agent ...

New

Senior Audio/Video Engineer

Sunnyvale, CA · On-site

$155K - $210K/yr

These engineers will be responsible for the full A/V stack - from WebRTC ingest and GStreamer ... Own the full audio subsystem: real-time two-way audio, SIP/VoIP integration (pjsip/Asterisk), text ...

Showing results 21-40

Sip Engineer information

See California salary details

$38.5K

$100.4K

$135.7K

How much do sip engineer jobs pay per year?

As of Aug 8, 2026, the average yearly pay for sip engineer in California is $100,420.00, according to ZipRecruiter salary data. Most workers in this role earn between $82,900.00 and $115,000.00 per year, depending on experience, location, and employer.

What are the typical daily responsibilities of a SIP engineer?

A SIP Engineer's daily tasks often include configuring, monitoring, and troubleshooting SIP-based communication systems, supporting VoIP infrastructure, and working on system integration with various platforms. They collaborate closely with network engineers, support teams, and sometimes clients to resolve complex issues, ensure call quality, and implement new features. Documentation, testing, and proactive network analysis are also regular parts of the role to help maintain optimal performance. This blend of technical and collaborative work offers variety each day and the opportunity to have a direct impact on critical business communications.

What is a SIP engineer?

A SIP Engineer is responsible for designing, implementing, and maintaining Session Initiation Protocol (SIP)-based communication systems. They work with VoIP technology, troubleshoot network issues, and ensure seamless integration of SIP services with existing telecommunication infrastructure. SIP Engineers collaborate with network administrators, developers, and vendors to optimize call quality, security, and system performance. Their role often includes configuring SIP trunks, monitoring traffic, and resolving service outages.

What are the key skills and qualifications needed to thrive in the SIP engineer position, and why are they important?

To excel as a SIP Engineer, you need a solid background in telecommunications networking, a deep understanding of Session Initiation Protocol (SIP), VoIP technologies, and often a degree in computer science or a related field. Experience with SIP protocol analyzers, network monitoring tools, and certifications such as CCNA or relevant VoIP certifications are commonly required. Outstanding troubleshooting skills, clear communication, and the ability to work effectively under pressure help set top performers apart. Mastery of these skills is critical to ensuring reliable and scalable communication services in dynamic telecom environments.

Infographic showing various Sip Engineer job openings in California as of August 2026, with employment types broken down into 81% Full Time, 13% Part Time, 2% Temporary, and 4% Contract. Highlights an 87% Physical, 4% Hybrid, and 9% Remote job distribution, with an average salary of $100,420 per year, or $48.3 per hour.

Chip Packaging Engineer 23-I

R2 Technologies Corporation

Mountain View, CA • On-site

$160K/yr

Full-time

Re-posted 9 days ago


Job description

Overview:
Job Title: Chip Packaging Engineer
Location: Mountain View, CA (Day 1 Onsite)
Experience level: 3 Years Candidate
Roles and Responsibilities
• 3 years' experience completing layouts of high pin count, multi-layer organic build-up packages using Cadence APD and SiP package design tools.
• Creating die and BGA symbols from scratch or from spreadsheet inputs
• Setting up design environment, including tech files, stack ups, and constraints
• Setting up Constraint Manager from scratch for complex packages (diff pair creaton, multiple power supplies, net and zone-specific constraints.
• Routing signals and matching length both manually and using tool features
• Design file management and documentation from initiation to final signoff
• Generation of POD
• Solid knowledge of top package suppliers design rules and basic manufacturing practices
Desired experience
• Experience with Cadence Orbit I/O
• 2.5D interposer design layout experience using Cadence SiP
• Experience with Virtuoso and/or Innovus for 2.5D interposer design
• Experience with Synopsys tools for 2.5D interposer design
• Experience writing and implementing custom scripts in Cadence tools
• Familiar with Cadence PVS
Education: Bachelor's Degree
Skills:
Developer,Aws,Azure