Silicon Design Engineer 2 Jobs (NOW HIRING)

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

THE ROLE: 

We are seeking a highly motivated Silicon Design Engineer. In this role, you will lead and contribute to the design, integration, verification, and characterization of advanced silicon testchips supporting FPGA and ASIC products on leading-edge process technologies

THE PERSON:

The ideal candidate is a hands-on silicon design engineer with experience across RTL-to-GDS implementation, design verification, and post-silicon validation. You should be comfortable working independently, driving technical challenges to closure, collaborating across teams, delivering successful tapeouts, and communicating effectively in fast-paced environments with a passion for innovation.

KEY RESPONSIBILITIES: 

• Drive the timing-aware/physical-aware synthesis flow using industry-standard tools (e.g., Design Compiler) to generate optimized netlists.
• Lead the end-to-end digital ASIC/SoC physical design cycle from RTL handoff through GDSII tapeout, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, signal integrity optimization, physical verification, and design signoff.
• Close SoC timing with Static Timing Analysis (STA) using tools such as PrimeTime to validate setup/hold margins across process, voltage, and temperature (PVT) corners.
• Drive tapeout readiness by performing physical signoff analyses including IR drop, electromigration (EM), noise, DRC/LVS verification, and cross-functional reviews with RTL, DFT, package, and foundry teams.
• Develop verification plans and testbenches to validate chip functionality, and generate test patterns for post-silicon validation
• Assist with postsilicon bring-up, debugging, and labbased validation activities.

PREFERRED EXPERIENCE: 

• Good understanding of CMOS circuit design fundamentals, semiconductor device physics, signal integrity, power integrity, and device reliability mechanisms.
• Proven experience delivering silicon across advanced process technologies, including FinFET (7nm/5nm/3nm) and emerging Gate-All-Around (GAA) nodes.
• Expertise in digital ASIC/SoC implementation flows, including synthesis, floorplanning, power planning, placement, CTS, routing, timing closure, and physical signoff using industry-standard tools (Cadence Genus/Innovus and/or Synopsys Fusion Compiler).
• Strong understanding of CMOS circuit design fundamentals, semiconductor device physics, signal integrity, power integrity, and device reliability mechanisms.
• Proven experience delivering silicon across advanced process technologies, including FinFET (7nm/5nm/3nm) and emerging Gate-All-Around (GAA) nodes.
• Hands-on experience with physical signoff methodologies, including STA, IR drop, electromigration (EM), DRC/LVS, noise analysis, and tapeout qualification.
• Strong analytical and problem-solving skills, with experience debugging complex design implementation issues and driving cross-functional closure.
• Experience with silicon bring-up, post-silicon validation, and laboratory test equipment is a plus.
• Proficiency in Python, Tcl, and shell scripting for automation, flow development, and productivity enhancement.

ACADEMIC CREDENTIALS: 

Preferably holds an advanced degree (PhD or MS) in electrical & electronics engineering or physical sciences; alternatively, a bachelor’s degree and relevant industry experience is acceptable.

This role is not eligible for visa sponsorship.

#LI-DR2

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.