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Serdes Manager Jobs (NOW HIRING)

Broadcom

High Speed SerDes DSP RTL Designer

San Jose, CA

$120K - $192K/yr

Broadcom is looking for a high-speed DSP SerDes RTL designer. Qualifications include: * MS or PhD ... Experience in design management with detailed knowledge of development methodologies, design flows ...

Apple

SerDes Circuit Design Engineer

Bodega Bay, CA

$126K - $220K/yr

While developing these complex IPs, on regular basis you will interact with your peers/management ... SerDes protocols (e.g., PCIe, USB, DP, MPHY) Skills in scripting and automation to enhance ...

Apple

SerDes Circuit Design Engineer

Waltham, MA

$114K - $199K/yr

While developing these complex IPs, on regular basis you will interact with your peers/management ... SerDes protocols (e.g., PCIe, USB, DP, MPHY) Skills in scripting and automation to enhance ...

Apple

SerDes Circuit Design Engineer

San Diego, CA

$120K - $210K/yr

While developing these complex IPs, on regular basis you will interact with your peers/management ... SerDes protocols (e.g., PCIe, USB, DP, MPHY) Skills in scripting and automation to enhance ...

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How much do serdes manager jobs pay per year?

As of Jun 7, 2026, the average yearly pay for serdes manager in the United States is $104,575.00, according to ZipRecruiter salary data. Most workers in this role earn between $114,000.00 and $116,500.00 per year, depending on experience, location, and employer.

What is a Serdes Manager?

A Serdes Manager is a professional responsible for overseeing the design, development, and integration of serializer/deserializer (SerDes) technology in electronic systems. SerDes technology is essential for high-speed data transmission between chips, boards, or systems, commonly used in data centers, telecommunications, and consumer electronics. The manager leads a team of engineers, coordinates project timelines, ensures compliance with industry standards, and collaborates with other departments to deliver reliable and efficient SerDes solutions. This role requires deep technical knowledge as well as strong leadership and project management skills.

What are the key skills and qualifications needed to thrive as a Serdes Manager, and why are they important?

To thrive as a Serdes Manager, you need a deep understanding of high-speed serial communication protocols, signal integrity, and experience in designing SerDes (Serializer/Deserializer) architectures, typically backed by a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), lab measurement equipment, and knowledge of standards like PCIe and Ethernet are essential, and certifications in project management or relevant technical areas can be advantageous. Exceptional leadership, communication, and problem-solving skills help manage cross-functional teams and drive project success. These combined skills ensure the efficient development of robust SerDes solutions that meet performance, reliability, and time-to-market goals in advanced technology environments.

What are some common challenges faced by a Serdes Manager in coordinating multidisciplinary teams?

A Serdes Manager often works with teams that include analog, digital, firmware, and validation engineers, which can sometimes lead to communication gaps and alignment issues. Managing project timelines while accommodating the different development cycles of each discipline is a frequent challenge. Additionally, ensuring that integration and verification processes run smoothly across hardware and software groups requires strong organizational and leadership skills. Building a collaborative environment and setting clear expectations are key to overcoming these challenges.
What are the most commonly searched types of Serdes jobs? The most popular types of Serdes jobs are:
Infographic showing various Serdes Manager job openings in the United States as of May 2026, with employment types broken down into 3% As Needed, 94% Part Time, 2% Temporary, and 1% Nights. Highlights an 87% Physical, 8% Hybrid, and 5% Remote job distribution, with an average salary of $104,575 per year, or $50.3 per hour.
High Speed SerDes DSP RTL Designer

High Speed SerDes DSP RTL Designer

Broadcom, Inc.

San Jose, CA

$120K - $192K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 29 days ago

Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

11th of 139 rated electronics manufacturers

Job description

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Job Description:
Broadcom is looking for a high-speed DSP SerDes RTL designer. Qualifications include:
  • MS or PhD in Electrical Engineering or Computer Engineering with 6+ years of experience in high speed ADC based SerDes RTL design.
  • Proficient with Verilog-HDL/System Verilog coding for PAM4 DSP based SerDes including equalization, adaptation and high-speed ADC calibration.
  • Proficient with front end tools such as NCVerilog, NCSIM, Simvision, Lint.
  • Exposure to Design for test, understanding of scan concept and writing DFT friendly RTL.
  • Deep understanding of high-speed serial interconnect architectures such as 100G/200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime.
  • Experience in synthesis, CDC, static timing analysis.
  • Exposure to SDF annotated simulations with good understanding of parasitic delays.
  • Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals.
  • Strong analytical thinking and problem-solving skills with excellent attention to details.
  • Must be organized, self-motivated and able to work effectively across internal and end customers teams.
  • Must have excellent knowledge/experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.

Highly Desired Qualifications:
- Understanding of micro architecture with standard peripherals such as AMBA BUS/I2C/SPI/UART.
- Deep understanding of Signal Integrity and Power Integrity modeling for High Speed designs.
- Understanding & exposure to verilog AMS simulation, experience in behavioral models of analog circuit will be helpful.
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $120,000 - $192,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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