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Serdes Manager Jobs (NOW HIRING)

Apple

SerDes Circuit Design Engineer

San Diego, CA · On-site

$214K/yr

While developing these complex IPs, on regular basis you will interact with your peers/management ... SerDes protocols (e.g., PCIe, USB, DP, MPHY) Skills in scripting and automation to enhance ...

Apple

SerDes Circuit Design Engineer

Austin, TX · On-site

While developing these complex IPs, on regular basis you will interact with your peers/management ... SerDes protocols (e.g., PCIe, USB, DP, MPHY) Skills in scripting and automation to enhance ...

Apple

SerDes Circuit Design Engineer

Beaverton, OR · On-site

While developing these complex IPs, on regular basis you will interact with your peers/management ... speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired Skills in scripting and ...

Apple

SerDes Circuit Design Engineer

Melbourne, FL · On-site

$187K/yr

While developing these complex IPs, on regular basis you will interact with your peers/management ... speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired Skills in scripting and ...

Apple

SerDes Circuit Design Engineer

Waltham, MA · On-site

While developing these complex IPs, on regular basis you will interact with your peers/management ... speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired Skills in scripting and ...

Apple

SerDes Circuit Design Engineer

Austin, TX · On-site

$200K/yr

While developing these complex IPs, on regular basis you will interact with your peers/management ... SerDes protocols (e.g., PCIe, USB, DP, MPHY) Skills in scripting and automation to enhance ...

Apple

SerDes Circuit Design Engineer

Austin, TX · On-site

While developing these complex IPs, on regular basis you will interact with your peers/management ... speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired Skills in scripting and ...

Apple Inc.

SerDes Circuit Design Engineer

Austin, TX · On-site

$200K/yr

While developing these complex IPs, on regular basis you will interact with your peers/management ... Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) * Skills in scripting ...

Apple

SerDes Circuit Design Engineer

Austin, TX

$200K/yr

While developing these complex IPs, on regular basis you will interact with your peers/management ... speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired Skills in scripting and ...

Apple

SerDes Circuit Design Engineer

Beaverton, OR · On-site

$210K/yr

While developing these complex IPs, on regular basis you will interact with your peers/management ... speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired Skills in scripting and ...

Apple

SerDes Circuit Design Engineer

Melbourne, FL · On-site

While developing these complex IPs, on regular basis you will interact with your peers/management ... speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired Skills in scripting and ...

Apple Inc.

SerDes Circuit Design Engineer

Cupertino, CA · On-site

$249K/yr

... SerDes team. Our team specializes in building next generation high-performance wireline ... While developing these complex IPs, on regular basis you will interact with your peers/management ...

Apple Inc.

SerDes Circuit Design Engineer

Waltham, MA · On-site

$116K - $203K/yr

... SerDes team! Our team specializes in building next generation high-performance wireline ... While developing these complex IPs, on regular basis you will interact with your peers/management ...

Apple

SerDes Circuit Design Engineer

Cupertino, CA

$184K - $324K/yr

While developing these complex IPs, on regular basis you will interact with your peers/management ... speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired Skills in scripting and ...

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Serdes Manager information

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$104.6K

$118K

How much do serdes manager jobs pay per year?

As of Sep 13, 2026, the average yearly pay for serdes manager in the United States is $104,575.00, according to ZipRecruiter salary data. Most workers in this role earn between $114,000.00 and $116,500.00 per year, depending on experience, location, and employer.

What is a Serdes manager?

A Serdes Manager is a professional responsible for overseeing the design, development, and integration of serializer/deserializer (SerDes) technology in electronic systems. SerDes technology is essential for high-speed data transmission between chips, boards, or systems, commonly used in data centers, telecommunications, and consumer electronics. The manager leads a team of engineers, coordinates project timelines, ensures compliance with industry standards, and collaborates with other departments to deliver reliable and efficient SerDes solutions. This role requires deep technical knowledge as well as strong leadership and project management skills.

What are the key skills and qualifications needed to thrive as a Serdes manager?

To thrive as a Serdes Manager, you need a deep understanding of high-speed serial communication protocols, signal integrity, and experience in designing SerDes (Serializer/Deserializer) architectures, typically backed by a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), lab measurement equipment, and knowledge of standards like PCIe and Ethernet are essential, and certifications in project management or relevant technical areas can be advantageous. Exceptional leadership, communication, and problem-solving skills help manage cross-functional teams and drive project success. These combined skills ensure the efficient development of robust SerDes solutions that meet performance, reliability, and time-to-market goals in advanced technology environments.

What are some common challenges faced by a Serdes manager in coordinating multidisciplinary teams?

A Serdes Manager often works with teams that include analog, digital, firmware, and validation engineers, which can sometimes lead to communication gaps and alignment issues. Managing project timelines while accommodating the different development cycles of each discipline is a frequent challenge. Additionally, ensuring that integration and verification processes run smoothly across hardware and software groups requires strong organizational and leadership skills. Building a collaborative environment and setting clear expectations are key to overcoming these challenges.

What are the most commonly searched types of Serdes jobs?

The most popular types of Serdes jobs are:

What are popular job titles related to Serdes Manager jobs?

For Serdes Manager jobs, the most frequently searched job titles are:

Infographic showing various Serdes Manager job openings in the United States as of September 2026, with employment types broken down into 86% Full Time, 13% Part Time, and 1% Contract. Highlights an 86% Physical, 2% Hybrid, and 12% Remote job distribution, with an average salary of $104,575 per year, or $50.3 per hour.

Principal Engineer, SerDes Validation

San Jose, CA • On-site

Ayar Labs
Computer and Peripheral Equipment Manufacturing • 51 - 200 employees
Learn more about Ayar Labsexternal

$180K - $230K/yr

Full-time

Re-posted 24 days ago

Job description

Principal Engineer, SerDes Validation
Location: San Jose (on-site)
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
We are seeking a System validation expert to spearhead the validation efforts that ensure our groundbreaking products meet and exceed both component and system-level requirements. This pivotal role will drive the transition of our technology from initial release to customer deployment, guaranteeing a seamless and high-performance experience for our clients.
If you are a seasoned validation expert who thrives on solving complex technical problems and is passionate about delivering high-quality products, we invite you to apply and join our team of innovators. Ayar Labs is pushing the boundaries of optical interconnect technology with our revolutionary multi-wavelength sources and CMOS chiplets.
Essential Functions:
  • Lead Validation Strategy: Define and implement comprehensive validation methodologies that guarantee high-speed performance of our optical chiplets, both at component and system-level. This includes developing test plans, defining success criteria, and selecting appropriate test equipment and methodologies.
  • Drive Product Bring-up: Collaborate with Design Engineering to bring up cutting-edge silicon photonic and laser products, troubleshooting and resolving complex technical issues on the optical SerDes devices.
  • Validate Component and System Performance: Perform rigorous design validation on new chips and products through high-speed characterization of electro-optic systems using signal integrity (SI) and eye analysis techniques.
  • Lead New Product Introduction (NPI): Collaborate with multi-disciplinary teams to identify and implement product improvements through bench characterization and ensure successful transition of products from development to mass production.
  • Deliver Customer-Ready Documentation: Author and maintain comprehensive customer-facing validation reports and documentation that clearly communicate product performance and reliability.
  • Develop Test Software and Infrastructure: Create and maintain software scripts and test hardware stations required for efficient and comprehensive validation.

Basic Qualifications:
  • Master's degree in Electrical Engineering or equivalent
  • 10+ years of experience with component and system test equipment (BERT, DCA, OSA, etc.) and standard signal quality metrics (TDECQ, SRS, URS).
  • 5+ years of experience in programming languages (Python, etc.) for test automation and data analysis.
  • Deep understanding of communication protocols and standards (Ethernet, PCIe, etc.).
  • Proven ability to analyze complex technical problems, identify root causes, and develop effective solutions.
  • Understanding of data analysis, process control, and statistical methods.
  • Experience with SoC validation planning, bring-up, debugging, and optimization.
  • Experience with high-speed SerDes and their characterization and optimization.

Preferred Qualifications:
  • Ph.D. in Electrical Engineering, Computer Science, Computer Engineering, or a related field.
  • 5+ years of hands-on experience in semiconductor laser & photonic device validation.
  • Working knowledge of optical transceiver packaging and integration challenges.
  • Strong project management and communication skills.

Salary range: $180,000 - $230,000
NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.
Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.

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