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Sram Circuit Design Engineer Jobs (NOW HIRING)

Geologics

Circuit Design Engineer

Orlando, FL · Hybrid

$71/hr

Circuit Design Engineer Client: Defense-Aerospace Hourly Rate: up to $71/hr (W2, non-benefited) Length: 1-year contract Location: Orlando, FL - Hybrid Shift: 4x10, 1st Shift Clearance: Due to the ...

Geologics

Circuit Design Engineer

Orlando, FL · Hybrid

$71/hr

Circuit Design Engineer Client: Defense-Aerospace Hourly Rate: up to $71/hr (W2, non-benefited) Length: 1-year contract Location: Orlando, FL - Hybrid Shift: 4x10, 1st Shift Clearance: Due to the ...

Nvidia

Senior Circuit Design Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

We are now hiring for a Senior Circuit Design Engineer for Standard Cell and/or ROM. NVIDIA has ... SRAM. * Strong proficiency in scripting language, such as, Perl, Tcl, Make, and automation methods ...

Lockheed Martin Corporation

As a Circuit Design Engineer, you will work on the development of a sophisticated state-of-the-art Avionics product in a world class Integrated Product Development environment. You will: Design ...

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SRAM Circuit Design Engineer information

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$149.5K

How much do sram circuit design engineer jobs pay per year?

As of Jul 22, 2026, the average yearly pay for sram circuit design engineer in the United States is $110,795.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,500.00 and $132,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an SRAM Circuit Design Engineer, and why are they important?

To thrive as an SRAM Circuit Design Engineer, you need a solid background in electrical engineering, semiconductor physics, and experience with digital and analog circuit design, typically supported by a relevant degree. Proficiency with EDA tools like Cadence, Synopsys, and Mentor Graphics, as well as familiarity with simulation, verification, and layout tools, is essential. Attention to detail, problem-solving skills, and the ability to communicate complex ideas clearly help engineers excel in collaborative and fast-paced environments. These skills are crucial for creating reliable, high-performance SRAM circuits that meet stringent power, area, and timing requirements in advanced chip designs.

What is the difference between Sram Circuit Design Engineer vs Digital Circuit Design Engineer?

AspectSram Circuit Design EngineerDigital Circuit Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, specialized in memory designBachelor's or Master's in Electrical Engineering or Computer Engineering
Work EnvironmentSemiconductor companies, memory chip manufacturersIntegrated circuit design firms, electronics companies
Industry UsageMemory and storage device industryGeneral digital electronics and integrated circuit industry

While both roles involve digital circuit design, a Sram Circuit Design Engineer specializes in designing SRAM memory cells and related circuitry, focusing on memory performance and stability. In contrast, a Digital Circuit Design Engineer works on a broader range of digital logic circuits, including processors, controllers, and other digital components. The roles share similar educational backgrounds and work environments but differ in their specific focus areas within digital electronics.

What does a SRAM Circuit Design Engineer do?

A SRAM Circuit Design Engineer is responsible for designing Static Random-Access Memory (SRAM) circuits used in various electronic devices such as processors and memory modules. Their work involves developing circuit architectures, performing simulations, and optimizing designs for speed, power, and reliability. They collaborate with layout engineers, verification teams, and manufacturing groups to ensure the SRAM functions correctly and efficiently in silicon. This role requires a strong understanding of CMOS technology, circuit analysis, and semiconductor fabrication processes.

What are some common challenges faced by SRAM Circuit Design Engineers during the development and verification process?

SRAM Circuit Design Engineers often encounter challenges such as balancing power, performance, and area (PPA) requirements while ensuring the memory cell's stability and reliability. Debugging issues related to leakage currents, process variations, and read/write margins is also frequent, requiring close collaboration with layout and verification teams. Additionally, engineers must stay up-to-date with evolving technology nodes and adapt their designs to meet stringent timing and yield goals. Effective communication with cross-functional teams is essential to address these complexities and deliver robust SRAM solutions.
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What cities are hiring for Sram Circuit Design Engineer jobs? Cities with the most Sram Circuit Design Engineer job openings:
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SRAM Circuit Design Engineer jobs near you
Infographic showing various Sram Circuit Design Engineer job openings in the United States as of July 2026, with employment types broken down into 83% Full Time, and 17% Contract. Highlights an 100% In-person job distribution, with an average salary of $110,795 per year, or $53.3 per hour.
Sr. SRAM Layout Design Engineer

Sr. SRAM Layout Design Engineer

USG, Inc.

Santa Clarita, CA • On-site

Other

Posted yesterday

USG rating

8.4

Company rating: 8.4 out of 10

Based on 57 frontline employees who took The Breakroom Quiz

50th of 534 rated manufacturers

Job description

Job Title: Sr. SRAM Layout Design Engineer

Location: Santa Clara, CA

Interview: Video Interview

Description:

SRAM 

Mixed signal Analog not needed

Min 10years experience 

What you will be doing:

· Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.

· Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.

· Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.

· Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.

· Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.

· Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.

· Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.

· Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.

· Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

What we need to see:

· Have a BSEE or equivalent experience

· 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.

· Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.

· Solid grasp of SRAM and memory layout principles.

· Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.

· Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.

· Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.

· Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.

· Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.

· Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.

· Knowledge of layout automation or AI tools is a definite plus.

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