IC/RTL Design Engineer
San Jose, CA ยท On-site
IC/RTL Design Engineer/ Front-End Engineer About the role. You design and implement the digital ... elastic FIFOs, and supporting logic. * Integrate IP and support parameterization for ...
San Jose, CA ยท On-site
IC/RTL Design Engineer/ Front-End Engineer About the role. You design and implement the digital ... elastic FIFOs, and supporting logic. * Integrate IP and support parameterization for ...
San Jose, CA ยท On-site
IC/RTL Design Engineer/ Front-End Engineer About the role. You design and implement the digital ... elastic FIFOs, and supporting logic. * Integrate IP and support parameterization for ...
Santa Clara, CA ยท On-site
$160K/yr
As a design engineer, you will prepare test methods and specifications, assist in preparation of ... logic design * Strong understanding of ASIC design flow from RTL to GDSII. * Familiarity with the ...
Santa Clara, CA ยท On-site
$160K/yr
As a design engineer, you will prepare test methods and specifications, assist in preparation of ... logic design * Strong understanding of ASIC design flow from RTL to GDSII. * Familiarity with the ...
As a design engineer, you will prepare test methods and specifications, assist in preparation of ... logic design * Strong understanding of ASIC design flow from RTL to GDSII. * Familiarity with the ...
As a design engineer, you will prepare test methods and specifications, assist in preparation of ... logic design * Strong understanding of ASIC design flow from RTL to GDSII. * Familiarity with the ...
South San Francisco, CA ยท On-site
$35/hr
Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ... Functional modeling experience and logic verification with SystemVerilog, SystemC/C++, or UVM
South San Francisco, CA ยท On-site
$35/hr
Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ... Functional modeling experience and logic verification with SystemVerilog, SystemC/C++, or UVM
Aliso Viejo, CA ยท On-site
$145K/yr
... core logic, memory subsystems, hardware security systems, peripheral interfaces, and power ... Experience developing system-level architecture and proposing RTL (Verilog) implementations with ...
Aliso Viejo, CA ยท On-site
$145K/yr
... core logic, memory subsystems, hardware security systems, peripheral interfaces, and power ... Experience developing system-level architecture and proposing RTL (Verilog) implementations with ...
$100K/yr
You will architect and design the digital IP, be responsible for the RTL implementation, perform ... Designing logic circuits with System Verilog/Verilog for implementing FSMs, arithmetic for digital ...
$100K/yr
You will architect and design the digital IP, be responsible for the RTL implementation, perform ... Designing logic circuits with System Verilog/Verilog for implementing FSMs, arithmetic for digital ...
Dallas, TX ยท On-site
$135K/yr
You will architect and design the digital IP, be responsible for the RTL implementation, perform ... Designing logic circuits with System Verilog/Verilog for implementing FSMs, arithmetic for digital ...
Dallas, TX ยท On-site
$135K/yr
You will architect and design the digital IP, be responsible for the RTL implementation, perform ... Designing logic circuits with System Verilog/Verilog for implementing FSMs, arithmetic for digital ...
Ridge, NY ยท On-site
$113K - $151K/yr
The IC Design Engineer will primarily use Cadence tools (Virtuoso, AMS, SpectreRF, Explorer, Assembler, Quantus, EMX, Physical Verification System) to complete the design tasks. Ansys HFSS may also ...
Ridge, NY ยท On-site
$113K - $151K/yr
The IC Design Engineer will primarily use Cadence tools (Virtuoso, AMS, SpectreRF, Explorer, Assembler, Quantus, EMX, Physical Verification System) to complete the design tasks. Ansys HFSS may also ...
Dallas, TX ยท On-site
$135K/yr
You will architect and design the digital IP, be responsible for the RTL implementation, perform ... Designing logic circuits with System Verilog/Verilog for implementing FSMs, arithmetic for digital ...
Dallas, TX ยท On-site
$135K/yr
You will architect and design the digital IP, be responsible for the RTL implementation, perform ... Designing logic circuits with System Verilog/Verilog for implementing FSMs, arithmetic for digital ...
Chestnut Ridge, NY ยท On-site
$113K - $151K/yr
Design for manufacturability and reliability The Tools The IC Design Engineer will primarily use Cadence tools (Virtuoso, AMS, SpectreRF, Explorer, Assembler, Quantus, EMX, Physical Verification ...
Chestnut Ridge, NY ยท On-site
$113K - $151K/yr
Design for manufacturability and reliability The Tools The IC Design Engineer will primarily use Cadence tools (Virtuoso, AMS, SpectreRF, Explorer, Assembler, Quantus, EMX, Physical Verification ...
Dallas, TX ยท On-site
$123K/yr
You will architect and design the digital IP, be responsible for the RTL implementation, perform ... A thorough understanding of digital logic design * Familiarity with the Verilog language and ...
Dallas, TX ยท On-site
$123K/yr
You will architect and design the digital IP, be responsible for the RTL implementation, perform ... A thorough understanding of digital logic design * Familiarity with the Verilog language and ...
Chestnut Ridge, NY ยท On-site
$113K - $151K/yr
Design for manufacturability and reliability The Tools The IC Design Engineer will primarily use Cadence tools (Virtuoso, AMS, SpectreRF, Explorer, Assembler, Quantus, EMX, Physical Verification ...
Chestnut Ridge, NY ยท On-site
$113K - $151K/yr
Design for manufacturability and reliability The Tools The IC Design Engineer will primarily use Cadence tools (Virtuoso, AMS, SpectreRF, Explorer, Assembler, Quantus, EMX, Physical Verification ...
Ridge, NY ยท On-site
$141K - $189K/yr
The Senior IC Design Engineer will collaborate closely with other members of the IC design team. Often, multiple designers are working together on one chip. Whether or not designers are working ...
Ridge, NY ยท On-site
$141K - $189K/yr
The Senior IC Design Engineer will collaborate closely with other members of the IC design team. Often, multiple designers are working together on one chip. Whether or not designers are working ...
Chandler, AZ ยท On-site
$133K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
Chandler, AZ ยท On-site
$133K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
... IC design methods. Minimum requirements: * Bachelors degree in Electrical or Computer Engineering ... Good understanding of digital logic design and familiarity with ASIC design flow from RTL to GDSII
... IC design methods. Minimum requirements: * Bachelors degree in Electrical or Computer Engineering ... Good understanding of digital logic design and familiarity with ASIC design flow from RTL to GDSII
Chandler, AZ ยท On-site
$133K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
Chandler, AZ ยท On-site
$133K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
Chandler, AZ ยท On-site
$133K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
Chandler, AZ ยท On-site
$133K/yr
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...
Minneapolis, MN ยท On-site
$130K - $150K/yr
Relevant circuits include ASIC library cells such as logic, registers, and I/O cells; memories; op ... Lead efforts to translate customer designs into ASIC technology (RTL to GDSII) * Execute and ...
Quick apply
Minneapolis, MN ยท On-site
$130K - $150K/yr
Relevant circuits include ASIC library cells such as logic, registers, and I/O cells; memories; op ... Lead efforts to translate customer designs into ASIC technology (RTL to GDSII) * Execute and ...
Hillsboro, OR ยท On-site
$141K - $200K/yr
Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly ... Develops the logic design, register transfer level (RTL) coding, and simulation for IP block.
Hillsboro, OR ยท On-site
$141K - $200K/yr
Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly ... Develops the logic design, register transfer level (RTL) coding, and simulation for IP block.
Senior Analog & Mixed Signal IC Design EngineerSenior Analog & Mixed Signal IC Design Engineer Get ... ago RTL Design Engineer, Hardware Compute Group San Jose, CA $145,000.00-$210,000.00 2 weeks ago ...
Senior Analog & Mixed Signal IC Design EngineerSenior Analog & Mixed Signal IC Design Engineer Get ... ago RTL Design Engineer, Hardware Compute Group San Jose, CA $145,000.00-$210,000.00 2 weeks ago ...
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
For Rtl Logic Ic Design Engineer jobs, the most frequently searched job titles are:

San Jose, CA โข On-site
Full-time
Re-posted 5 days ago