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Rtl Logic Ic Design Engineer Jobs (NOW HIRING)

IC/RTL Design Engineer/ Front-End Engineer About the role. You design and implement the digital ... elastic FIFOs, and supporting logic. * Integrate IP and support parameterization for ...

Digital IC Design Engineer

Santa Clara, CA ยท On-site

$160K/yr

As a design engineer, you will prepare test methods and specifications, assist in preparation of ... logic design * Strong understanding of ASIC design flow from RTL to GDSII. * Familiarity with the ...

Digital IC Design Engineer

Aliso Viejo, CA ยท On-site

$145K/yr

... core logic, memory subsystems, hardware security systems, peripheral interfaces, and power ... Experience developing system-level architecture and proposing RTL (Verilog) implementations with ...

$100K/yr

You will architect and design the digital IP, be responsible for the RTL implementation, perform ... Designing logic circuits with System Verilog/Verilog for implementing FSMs, arithmetic for digital ...

IC Design Engineer

Ridge, NY ยท On-site

$113K - $151K/yr

The IC Design Engineer will primarily use Cadence tools (Virtuoso, AMS, SpectreRF, Explorer, Assembler, Quantus, EMX, Physical Verification System) to complete the design tasks. Ansys HFSS may also ...

IC Design Engineer

Chestnut Ridge, NY ยท On-site

$113K - $151K/yr

Design for manufacturability and reliability The Tools The IC Design Engineer will primarily use Cadence tools (Virtuoso, AMS, SpectreRF, Explorer, Assembler, Quantus, EMX, Physical Verification ...

IC Design Engineer

Chestnut Ridge, NY ยท On-site

$113K - $151K/yr

Design for manufacturability and reliability The Tools The IC Design Engineer will primarily use Cadence tools (Virtuoso, AMS, SpectreRF, Explorer, Assembler, Quantus, EMX, Physical Verification ...

Senior IC Design Engineer

Ridge, NY ยท On-site

$141K - $189K/yr

The Senior IC Design Engineer will collaborate closely with other members of the IC design team. Often, multiple designers are working together on one chip. Whether or not designers are working ...

Digital Design Engineer

Chandler, AZ ยท On-site

$133K/yr

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...

Staff Digital Design Engineer

Chandler, AZ ยท On-site

$133K/yr

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...

Senior Digital Design Engineer

Chandler, AZ ยท On-site

$133K/yr

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Develop RTL designs using Verilog and support integration into larger SoC environments. * Design ...

Sr. Logic Design Engineer

Hillsboro, OR ยท On-site

$141K - $200K/yr

Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly ... Develops the logic design, register transfer level (RTL) coding, and simulation for IP block.

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Rtl Logic Ic Design Engineer information

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$88.2K

$158.5K

How much do rtl logic ic design engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for rtl logic ic design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

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Infographic showing various Rtl Logic Ic Design Engineer job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $88,150 per year, or $42.4 per hour.

IC/RTL Design Engineer

San Jose, CA โ€ข On-site

Full-time

Re-posted 5 days ago


Job description

IC/RTL Design Engineer/ Front-End Engineer
About the role. You design and implement the digital front-end RTL at the heart of the chip - including the high-speed datapath that moves data between UCIe and the optical front end. Guided by the interface specs and coding standards, you take blocks from micro-architecture through clean, timing-aware RTL and block-level verification. It's a hands-on role with room to grow your scope as the team and the chip mature.
What you'll do
  • Develop block-level micro-architecture for your assigned blocks, and contribute to interface and register definitions.
  • Design and implement front-end RTL blocks in SystemVerilog - datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.
  • Integrate IP and support parameterization for configurability.
  • Write clean, lint-clean, CDC/RDC-clean RTL that follows the coding and quality standards.
  • Write block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before handoff to DV.
  • Power- and timing-aware design - managing block activity, clock-gating, pipelining, and retiming; partner with the backend team on physical closure for your blocks.
  • Bring-up and debug across simulation and emulation / FPGA prototyping; support DV and silicon bring-up, including DFT/debug hooks in your blocks.
  • Collaborate with the architecture, modelling, DV, DFT, and backend teams as your blocks move through the flow.

Required
  • BS or MS in Electrical/Computer Engineering (or equivalent experience).
  • 3+ years of digital RTL design in SystemVerilog, with blocks taken from micro-architecture through to verification handoff.
  • Solid digital design fundamentals: pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI).
  • Lint and CDC/RDC discipline and clean-RTL practices.
  • Power- and timing-aware design practices; comfort with synthesis and timing closure, working with the backend team.
  • Strong debug skills in simulation; scripting in Python, Perl, or TCL.

Preferred
  • High-speed datapath, SerDes-adjacent, or interface design exposure (UCIe, PCIe/CXL, or similar).
  • FEC/coding datapath familiarity (e.g., Reed-Solomon) and gray-code mapping.
  • Assertion-based verification (SVA) and familiarity with UVM block-level testbenches; emulation / FPGA prototyping experience.
  • Exposure to scale-up / scale-out interconnects or network switch / NIC / memory-controller datapaths.
  • Low-power / UPF and DFT (scan) concepts.
  • Optical transceiver, CPO, or linear-drive optics background; advanced-node (N5/N3/N2) design experience.