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Rtl Design Verification Engineer Jobs (NOW HIRING)

Design Verification Engineer

San Jose, CA ยท On-site

$159K - $194K/yr

You'll build SystemVerilog and UVM verification environments alongside architects, RTL designers ... looking for a talented and motivated Design Verification Engineer, DFT to help us build ...

C - Focused Design Verification Engineer

San Diego, CA ยท On-site

$144K - $176K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description As a C- Focused Design Verification Engineer, you will be at the center of a chip ...

Design Verification Engineer

Austin, TX ยท On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key ... DV engineers collaborate with many teams, including RTL design, architecture modeling, custom ...

Design Verification Engineer

Austin, TX ยท On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key ... DV engineers collaborate with many teams, including RTL design, architecture modeling, custom ...

Design Verification Engineer

Austin, TX ยท On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key ... DV engineers collaborate with many teams, including RTL design, architecture modeling, custom ...

Design Verification Engineer

Palo Alto, CA ยท On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key ... DV engineers collaborate with many teams, including RTL design, architecture modeling, custom ...

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key ... DV engineers collaborate with many teams, including RTL design, architecture modeling, custom ...

Design Verification Engineer

Broomfield, CO ยท On-site

$108K - $172K/yr

Design Verification Engineer Broadcom's ASIC Products Division (APD) is looking for an experienced ... Ensure knowledge of RTL, gate-level netlists, SDF, and debug such formats. Qualifications * 6+ ...

Design Verification Engineer

Santa Clara, CA ยท On-site

$159K - $195K/yr

We are seeking a skilled Design Verification Engineer to join our hardware engineering team. The ... Solid understanding of digital design fundamentals (RTL, timing, clocking). * Experience with EDA ...

Principal ASIC Design Verification Engineer

OR ยท On-site +1

$190K - $285K/yr

You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...

Senior Design Verification Engineer

Austin, TX ยท On-site

$120K - $225K/yr

DV engineers collaborate closely with RTL design, architecture modeling, custom analog IP, compiler ... Creation of verification infrastructure and flows. * Leverage architecture models and emulation ...

DV engineers collaborate closely with RTL design, architecture modeling, custom analog IP, compiler ... Creation of verification infrastructure and flows. * Leverage architecture models and emulation ...

Showing results 41-60

Rtl Design Verification Engineer information

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$105.5K

$149.2K

$167K

How much do rtl design verification engineer jobs pay per year?

As of Sep 14, 2026, the average yearly pay for rtl design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

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States with the most job openings for Rtl Design Verification Engineer jobs include:

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Design Verification Engineer

San Jose, CA โ€ข On-site

$159K - $194K/yr

Full-time

Posted 26 days ago


Job description

About the team

The Design Verification team works on the RDU, SambaNova's chip for machine learning and AI workloads. This group focuses on chip-level control and initialization: sequencing, state transitions, clocking, and recovery across multiple subsystems on the chip. You'll build SystemVerilog and UVM verification environments alongside architects, RTL designers, and firmware engineers, and take ownership of verification plans from first draft through closure. The team works closely with the broader verification organization, so debugging and root-causing issues often means coordinating across groups rather than working in isolation.

About the role

SambaNova Systems is looking for a talented and motivated Design Verification Engineer, DFT to help us build state of the art RDU chips for machine learning and artificial intelligence.

Responsibilities
  • Develop and execute comprehensive verification plans for complex chip-level control and initialization features
  • Develop SystemVerilog/UVM based verification environments, test sequences, checkers, assertions, and functional coverage
  • Verify complex sequencing, dependencies, state transitions, and recovery scenarios across multiple chip subsystems
  • Develop directed and constrained-random tests to identify architectural and implementation corner cases
  • Closely work with architects, RTL designers, firmware, and other verification teams to understand design intent and drive verification closure
  • Debug simulation and regression failures and work with design teams to root-cause and resolve issues
  • Analyze regression failures, functional and code coverage and drive verification to closure
Required Qualifications
  • B.S. in Computer Science, Computer Engineering, or related field
  • 5+ years relevant industry experience
  • Strong understanding of digital design, SoC architecture, and verification methodologies
  • Strong proficiency in SystemVerilog and UVM is required
  • Experience with constrained-random verification, functional coverage, and assertion-based verification
  • Good understanding of chip initialization, control sequencing, clocking, and cross-domain interactions
  • Strong simulation debug and problem-solving skills
  • Proficiency in scripting languages, e.g. Python, Perl, TCL and shell scripting, etc. is required
Preferred Qualifications
  • Familiarity with CDC/RDC concepts and verification methodologies
  • Fluency in Claude / AI tools for verification development and debug
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