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Rtl Design Verification Engineer Jobs (NOW HIRING)

RTL Verification Engineer

Santa Clara, CA ยท On-site

$158K - $193K/yr

We are looking for an experienced RTL Verification Engineer with strong expertise in DFX (Design for X), VISA/Debug, JTAG, and ASIC/SoC verification . The ideal candidate will have hands-on ...

RTL Design/AMS Verification Engineer

Richardson, TX ยท On-site +1

$122K - $149K/yr

We are seeking an experienced RTL Design / AMS Verification Engineer to support digital and mixed-signal IC development from architecture through implementation and verification. The ideal candidate ...

Design Verification Engineer

San Jose, CA ยท On-site

$159K - $194K/yr

Etched Design Verification Engineer 6 Openings Location: San Jose, CA & Austin, TX - onsite Please ... You collaborate naturally with cross-functional teams from RTL design to software and emulation and ...

Design Verification Engineer

San Diego, CA ยท On-site

$144K - $176K/yr

Design Verification Engineer Job Type : Full time Location : San Diego And Bay Area : Strong ... RTL design experience and/or very strong OOPs programming experience is also a plus. Good written ...

Design Verification Engineer

Plano, TX ยท On-site

$130K - $158K/yr

You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...

Design Verification Engineer

Austin, TX ยท On-site

$134K - $164K/yr

Experience in other related domains such as formal verification, RTL design, or software development EDUCATION: Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer ...

Wireless Design Verification Engineer

San Francisco, CA ยท On-site

$160K - $195K/yr

As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. You will interact with DV ...

PHY Design Verification Engineer

San Francisco, CA ยท On-site

$160K - $195K/yr

As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will interact ...

Wireless Design Verification Engineer

San Francisco, CA ยท On-site

$160K - $195K/yr

As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. You will interact with DV ...

Design Verification Engineer

Austin, TX ยท On-site

$134K - $164K/yr

Experience in other related domains such as formal verification, RTL design, or software development EDUCATION: Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer ...

PHY Design Verification Engineer

San Francisco, CA ยท On-site

$160K - $195K/yr

As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will interact ...

Senior Design Verification Engineer

Austin, TX ยท On-site

$134K - $164K/yr

Experience in other related domains such as formal verification, RTL design, or software development EDUCATION: Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer ...

Job Title:Power Engineer (RTL Design) Location:Sunnyvale CA or Austin TX Duration: Long term ... Please look for design engineers with power analysis experience Verification engineers with power ...

Senior Design Verification Engineer

Austin, TX ยท On-site

$134K - $164K/yr

Experience in other related domains such as formal verification, RTL design, or software development EDUCATION: Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer ...

Design Verification Engineer

San Diego, CA ยท On-site

$144K - $176K/yr

Design Verification Engineer Location: Bay Area, CA (Onsite/Hybrid) Experience: 8+ Years Job ... Debug RTL and simulation issues in collaboration with design teams. * Verify complex IPs and SoCs ...

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Rtl Design Verification Engineer information

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$105.5K

$149.2K

$167K

How much do rtl design verification engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for rtl design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

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States with the most job openings for Rtl Design Verification Engineer jobs include:

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For Rtl Design Verification Engineer jobs, the most frequently searched job titles are:

RTL Verification Engineer

Santa Clara, CA โ€ข On-site

$158K - $193K/yr

Other

Posted 12 days ago


Job description

We are looking for an experienced RTL Verification Engineer with strong expertise in DFX (Design for X), VISA/Debug, JTAG, and ASIC/SoC verification. The ideal candidate will have hands-on experience developing and executing verification environments for debug logic, DFX features, scan/debug interfaces, and related RTL.

DFX โ€“ RTL Verification Engineer | VISA / JTAG / Debug Validation

Location: Santa Clara, CA
Duration: 12 Months

Key Responsibilities & Requirements

  • 6 โ€“ 8  years of hands-on experience in RTL Design Verification, DFX Verification, or ASIC/SoC Verification.
  • Strong experience in DFX (Design for X) verification and validation of DFX-related RTL.
  • Hands-on experience with JTAG / IEEE 1149.x architecture, TAP controllers, and boundary-scan concepts.
  • Strong knowledge of VISA (Vendor Independent Silicon Architecture) / VISA Debug and related validation methodologies.
  • Experience validating debug logic, debug access mechanisms, scan/debug interfaces, and associated RTL.
  • Strong hands-on expertise in SystemVerilog and UVM.
  • Experience developing and maintaining UVM testbenches, test scenarios, assertions, functional coverage, and verification plans.
  • Hands-on experience with simulation, waveform/debug analysis, failure investigation, and root-cause analysis.
  • Experience working within complex ASIC/SoC verification environments.
  • Good understanding of DFT/DFX concepts, scan architectures, TAP controllers, JTAG, and boundary scan.
  • Strong scripting/programming skills using Python, Perl, Tcl, or similar languages.
  • Experience with industry-standard verification and debug tools such as Synopsys VCS/Verdi, Siemens Questa/ModelSim, or equivalent is preferred.

 

Ideal Candidate

The ideal candidate should be able to independently drive DFX/VISA/JTAG verification activities, develop robust SystemVerilog/UVM-based verification environments, debug complex RTL failures, and work closely with Design, DFT, Architecture, and Silicon Validation teams.