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Rf Analog Ic Design Engineer Jobs (NOW HIRING)

Nokia

Senior Analog EDA/CAD ASIC Engineer

Sunnyvale, CA · On-site

$120K - $171K/yr

High-Speed Analog EDA/CAD Engineer: Brief Description: Full-time position. Infinera is seeking an ... Install, customize and support Custom IC and RF CAD environment for the design of high-speed (10-40 ...

Apple

Analog IC Design Engineer

Cupertino, CA · On-site

$129K - $225K/yr

Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures ... production test engineers to firm up test plans and design for testability details Minimum ...

Apple

Analog IC Design Engineer

Cupertino, CA

$184K - $324K/yr

Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures ... production test engineers to firm up test plans and design for testability details Minimum ...

Apple

Analog IC Design Engineer

Cupertino, CA

$184K - $324K/yr

Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures ... production test engineers to firm up test plans and design for testability details Minimum ...

Apple

Analog IC Design Engineer

Cupertino, CA

$184K - $324K/yr

Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures ... production test engineers to firm up test plans and design for testability details Minimum ...

Apple Inc.

Analog IC Design Engineer

San Diego, CA · On-site

$171.60 - $302.20/hr

Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures ... Design for ESD compliance. Minimum Qualifications * Bachelor's of Science in Electrical Engineering ...

Apple

Analog IC Design Engineer

Cupertino, CA

$184K - $324K/yr

Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures ... production test engineers to firm up test plans and design for testability details Minimum ...

Apple

Analog IC Design Engineer

Cupertino, CA

$184K - $324K/yr

Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures ... production test engineers to firm up test plans and design for testability details Minimum ...

Apple

Analog IC Design Engineer

Cupertino, CA

$175K - $308K/yr

Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures ... production test engineers to firm up test plans and design for testability details Minimum ...

Apple

Analog IC Design Engineer

Cupertino, CA

$129K - $225K/yr

Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures ... production test engineers to firm up test plans and design for testability details Minimum ...

Qorvo, Inc.

$120 - $180/hr

Senior Analog/RF/Mixed-Signal IC Design Engineer Summary As a Senior Analog/RF/Mixed-Signal IC Design Engineer, you will work as part of a cross-functional, global team delivering System-on-Chip (SoC ...

Apple Inc.

Analog IC Design Engineer

Sunnyvale, CA · On-site

$129.30 - $225.30/hr

Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures ... Design for ESD compliance. Minimum Qualifications * Bachelor's of Science in Electric Engineering ...

Qorvo, Inc.

NY · On-site

$120 - $180/hr

Senior Analog/RF/Mixed-Signal IC Design Engineer Summary As a Senior Analog/RF/Mixed-Signal IC Design Engineer, you will work as part of a cross-functional, global team delivering System-on-Chip (SoC ...

Apple

Analog IC Design Engineer

Cupertino, CA

$129K - $225K/yr

Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures ... production test engineers to firm up test plans and design for testability details Minimum ...

Apple

Analog IC Design Engineer

Cupertino, CA

$175K - $308K/yr

Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures ... production test engineers to firm up test plans and design for testability details Minimum ...

Apple

Analog IC Design Engineer

Cupertino, CA

$175K - $308K/yr

Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures ... production test engineers to firm up test plans and design for testability details Minimum ...

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Rf Analog Ic Design Engineer information

See salary details

$77K

$186.2K

$203K

How much do rf analog ic design engineer jobs pay per year?

As of Sep 5, 2026, the average yearly pay for rf analog ic design engineer in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.

What is an RF Analog IC Design engineer?

RF Analog IC Design Engineers are professionals who design integrated circuits (ICs) that operate at radio frequencies (RF). Their work involves creating circuits for devices such as wireless communication systems, radar, and radio transmitters and receivers. These engineers use their knowledge of analog electronics and electromagnetic theory to develop high-performance, low-noise, and energy-efficient chips. They often collaborate with layout engineers and test engineers to ensure the final IC meets all specifications. Their expertise is crucial in enabling reliable wireless communication in modern electronic devices.

What are the key skills and qualifications needed to thrive as an RF Analog IC Design engineer?

To thrive as an RF Analog IC Design Engineer, you need a solid background in electrical engineering, semiconductor physics, and RF circuit design, typically supported by a relevant engineering degree. Familiarity with EDA tools like Cadence Virtuoso, SPICE simulation, and RF measurement equipment, as well as knowledge of industry standards, is essential. Strong problem-solving, attention to detail, and effective teamwork skills distinguish top performers in this field. These competencies are crucial for developing high-performance, reliable integrated circuits that meet stringent technical and commercial requirements.

What are some common challenges faced by RF Analog IC Design engineers during the design and testing phases?

RF Analog IC Design Engineers often encounter challenges such as managing signal integrity, minimizing noise and interference, and optimizing power consumption while meeting strict performance specifications. The complexity of high-frequency circuit behavior requires careful simulation, layout, and validation to ensure designs function as intended in real-world environments. Collaboration with layout engineers, test engineers, and system architects is essential to troubleshoot issues and refine designs, making strong communication and problem-solving skills crucial for success in this role.

What is the difference between Rf Analog Ic Design Engineer vs RF Circuit Design Engineer?

AspectRf Analog Ic Design EngineerRF Circuit Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering, specialized in RF/Analog designBachelor's or Master's in Electrical Engineering, with focus on RF circuits
Work EnvironmentDesign labs, semiconductor companies, integrated circuit manufacturingResearch labs, semiconductor firms, wireless device companies
Industry UsageDesigning integrated RF analog components for chipsDeveloping RF circuits for wireless systems and devices

While both roles focus on RF and analog design, the Rf Analog Ic Design Engineer specializes in designing integrated RF analog circuits within chips, whereas the RF Circuit Design Engineer may work on broader RF circuit development for various wireless applications. The roles often overlap but differ mainly in scope and focus within the RF design process.

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Rf Analog Ic Design Engineer jobs near you
Infographic showing various Rf Analog Ic Design Engineer job openings in the United States as of August 2026, with employment types broken down into 90% Full Time, 7% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $186,238 per year, or $89.5 per hour.

Senior Analog EDA/CAD ASIC Engineer

Nokia

Sunnyvale, CA • On-site

$120K - $171K/yr

Full-time

Medical, Dental, Life, Retirement, PTO

Re-posted 18 days ago

Nokia rating

7.9

Company rating: 7.9 out of 10

Based on 6 frontline employees who took The Breakroom Quiz

30th of 101 rated telecommunications companies

Job description


High-Speed Analog EDA/CAD Engineer:
Brief Description: Full-time position.
Infinera is seeking an EDA/CAD Engineer to support SiGE and CMOS research & development and chip design in the Optical Modules Group (OMG) located in Sunnyvale, CA.
Description:
Infinera is seeking an EDA/CAD Engineer to support and develop SiGe and CMOS design solutions for the high speed analog ASIC design team. The engineer will be hands-on with all phases of tool flow including foundry interface, PDK installation and support, tool evaluation and installation, layout, archive and tapeout. The engineer must be an expert in analog and mixed-signal circuit design flows and tools. Tasks will include significant tool and PDK customization and design team support. The self-motivated engineer must be able to anticipate problems and devise effective solutions.
Responsibilities:
  • Install, customize and support external vendor PDK's for both SiGe and CMOS processes
  • Install, customize and support Custom IC and RF CAD environment for the design of high-speed (10-40 Gb/s), broad-band, mixed-signal, integrated circuits for fiber-based wireline applications.
  • Lead and contribute to the development of design standards, IC development processes, CAD tools and design flows.
  • Execute and support layout efforts including archive and tapeout processes

Minimum Expertise Requirements:
  • Expert in high-speed analog and mixed-signal IC design concepts and must demonstrate superior critical thinking skills, problem solving capabilities and engineering judgment.
  • Fluent with analog EDA front and back end tools
    • Cadence Virtuoso, ADE
    • Strong SKILL programming a must
    • Mentor Calibre (end user support and rule deck writing)
  • Detailed understanding of advanced high-speed analog & mixed-signal layout concepts
  • FlexLM license management
  • Strong UNIX/Linux knowledge
  • Not required but preferred
    • Perforce
    • Ocean scripting and advanced modelling and simulation knowledge
    • Linux OS support

Minimum Experience Requirements:
  • 5 years of experience working as a high-speed analog & mixed signal IC CAD professional is required
  • IC Technologies: High-speed IC technologies, including CMOS and bipolar.
  • IC Design Software:
    • Experience with configuring, documenting, and maintaining high speed analog IC design flows is a must.
    • Experience with transistor-level IC design and verification software, e.g. Cadence Composer, Cadence Virtuoso, Cadence Spectre, Virtuoso AMS, Mentor Calibre, Skill language, is a must.
  • General understanding of digital physical design flows, e.g. RTL coding, place and route, DRC/LVS verification.
  • Work Environment: Comfortable working in a fast-paced environment. Must be strong individual contributor, and also able to work as member of a small team. Must be able to support EPDA users and solve problems efficiently, effectively and rapidly.

Education Requirements:
  • BS 5+ years
  • MS 4+ years
  • PhD 3+ years

Responsibilities
  • Install, customize and support external vendor PDK's for both SiGe and CMOS processes
  • Install, customize and support Custom IC and RF CAD environment for the design of high-speed (10-40 Gb/s), broad-band, mixed-signal, integrated circuits for fiber-based wireline applications.
  • Lead and contribute to the development of design standards, IC development processes, CAD tools and design flows.
  • Execute and support layout efforts including archive and tapeout processes

Qualifications
  • 5 years of experience working as a high-speed analog & mixed signal IC CAD professional is required
  • IC Technologies: High-speed IC technologies, including CMOS and bipolar.
  • IC Design Software:
    • Experience with configuring, documenting, and maintaining high speed analog IC design flows is a must.
    • Experience with transistor-level IC design and verification software, e.g. Cadence Composer, Cadence Virtuoso, Cadence Spectre, Virtuoso AMS, Mentor Calibre, Skill language, is a must.
  • General understanding of digital physical design flows, e.g. RTL coding, place and route, DRC/LVS verification.
  • Work Environment: Comfortable working in a fast-paced environment. Must be strong individual contributor, and also able to work as member of a small team. Must be able to support EPDA users and solve problems efficiently, effectively and rapidly.

About Us
Advancing connectivity to secure a brighter world.
Nokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we're advancing connectivity to secure a brighter world.
Learn more about life at Nokia.
Our recruitment process
We act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.
If you're interested in this role but don't meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.
The length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.
About the Team
Some of our benefits in US:
  • Corporate Retirement Savings Plan
  • Health and dental benefits
  • Short-term disability, and long-term disability
  • Life insurance, and AD&D - Company paid 2x base pay
  • Optional or Supplemental life and AD&D insurance (Employee/Spouse/Child)
  • Paid time off for holidays and Vacation
  • Employee Stock Purchase Plan
  • Tuition Assistance Plan
  • Adoption assistance
  • Employee Assistance Program/Work Life Resource Program

The above benefits exclude students.
Disclaimer for US/Canada
Nokia Maintains broad annual base salary ranges for its roles in order to account for variations in knowledge, skills, experience and market conditions, and with consideration to internal peer equity. Check the salary ranges in the job info section for this role.
All North America job posts will post for a minimum of 7 calendar days and up to 180 days or until candidate/s identified.

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