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As of Aug 8, 2026, the average hourly pay for random in Virginia is $23.38, according to ZipRecruiter salary data. Most workers in this role earn between $18.12 and $26.20 per hour, depending on experience, location, and employer.

What is a random?

Random jobs refer to a variety of employment opportunities that do not fit into a specific category or industry. These jobs can range from temporary gigs and part-time positions to freelance work and odd jobs that people take on for extra income or experience. Random jobs are often flexible, may not require specialized skills or education, and can provide a way to explore different fields or supplement other income sources. Examples might include pet sitting, delivery driving, online surveys, event staffing, or handyman tasks. They are ideal for individuals seeking flexibility or those looking to try out different types of work.
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Infographic showing various Random job openings in Virginia as of July 2026, with employment types broken down into 72% Full Time, 22% Part Time, and 6% Contract. Highlights an 98% In-person, and 2% Remote job distribution, with an average salary of $48,622 per year, or $23.4 per hour.

FPGA Verification Engineer with Security Clearance

Legacy Consulting Services , LLC

Arlington, VA • On-site

$141K - $195K/yr

Other

Re-posted 8 days ago

Job description

Location: Arlington, VA (HQ2) or Jessup, MD Clearance: Active TS/SCI with polygraph required Citizenship: US Citizen required Scope of Work
Develop and execute verification strategies for FPGA-based systems supporting AWS infrastructure. The contractor will build UVM-based verification environments, develop testbenches, and drive coverage closure for 100G+ networking solutions on advanced FPGA platforms. Key Responsibilities
• Develop UVM/SystemVerilog verification environments and testbenches for FPGA designs
• Create and execute verification plans with functional coverage models and assertions
• Drive coverage closure to completion (functional, code, and assertion coverage)
• Debug RTL failures in simulation and on hardware targets
• Develop constrained-random and directed test sequences for protocol verification (e.g., AXI, Ethernet)
• Perform regression analysis and coverage gap identification
• Collaborate with design engineers on architecture reviews and interface specifications
• Support hardware bring-up and debug on FPGA targets Required Qualifications
• BS in Electrical Engineering or related field
• 5+ years FPGA/ASIC verification experience
• SystemVerilog required
• 5+ years with UVM-based verification (constrained-random, coverage-driven methodologies)
• Demonstrated experience driving coverage closure to completion
• Strong UVM testbench architecture skills (agents, sequences, scoreboards, coverage models)
• Proficiency in SystemVerilog assertions (SVA) and simulation tools (Synopsys VCS, Mentor Questa, or equivalent)
• Experience verifying high-speed networking or datapath designs
• Knowledge of standard bus protocols (AXI, AXI-Stream, Ethernet)
• Active TS/SCI with polygraph (US Citizen)

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