Prototype Engineer Jobs in California (NOW HIRING)

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As a member of the front‑end design and integration team, you will help bring cutting‑edge silicon designs to life. Working closely with Architecture, IP Design, Physical Design, Verification, Software, and Product Engineering teams, you will drive FPGA prototyping strategy and execution to enable first‑pass silicon success.

The ideal candidate is a highly experienced FPGA prototyping engineer with strong technical leadership skills. You are detail‑oriented, collaborative, and capable of driving complex technical initiatives while mentoring engineering teams and influencing cross‑functional stakeholders.

• Define and own the FPGA prototyping architecture, methodology roadmap, and platform strategy for complex SoCs, including partitioning, interconnects, clocking, debug infrastructure, and high‑speed interfaces.
• Lead the development and deployment of FPGA prototype platforms, including RTL adaptation, implementation flows, verification infrastructure, regression environments, and system‑level debug capabilities.
• Drive collaboration across Architecture, RTL Design, Verification, Emulation, Software, and Firmware teams to enable early hardware validation, software bring‑up, and functional coverage goals.
• Provide technical leadership for FPGA prototyping engineers through mentoring, design reviews, best‑practice development, project planning, and execution of key program milestones.
• Establish engineering processes, implementation methodologies, documentation standards, and continuous improvement initiatives to improve efficiency, quality, and scalability.
• Represent the FPGA prototyping organization in architecture reviews, program reviews, and customer‑facing technical discussions while partnering with EDA and FPGA tool vendors to drive technology adoption and resolve complex technical challenges.

• 12+ years of experience in FPGA design, implementation, and SoC prototyping.
• Proven experience leading FPGA prototyping efforts for large‑scale semiconductor programs.
• Hands‑on experience with Synopsys HAPS and/or Cadence Protium platforms.
• Strong knowledge of multi‑FPGA partitioning, board bring‑up, and high‑speed interfaces such as PCIe, DDR, Ethernet, USB, and HBM.
• Expert proficiency with AMD/Xilinx Vivado and Vitis toolchains.
• Deep expertise in FPGA timing closure, floorplanning, CDC analysis, pipelining, and performance optimization.
• Strong SystemVerilog and/or Verilog design and verification experience.
• Solid understanding of modern SoC architectures, including CPUs, cache hierarchies, memory subsystems, NoC/interconnects, and I/O protocols such as AXI, ACE, CHI, PCIe, and DDR.

Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

San Jose, CA

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.