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Professional Cadence Design Jobs (NOW HIRING)

Cadence Design Systems Inc.

$92K - $171K/yr

... PCB Design is required 5+ years experience with Cadence SI/PI tools Allegro platform tools ... continuous learning and expanding professional skill sets Excellent verbal and written ...

Cadence Design Systems Inc.

Solutions Architect

Cary, IL · On-site +1

$148K - $275K/yr

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of ... Bachelor's degree with at least 16-25 years of design/EDA experience or Master's degree with at ...

Cadence Design Systems Inc.

Solutions Architect

Home, WA · On-site +1

$148K - $275K/yr

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of ... Bachelor's degree with at least 16-25 years of design/EDA experience or Master's degree with at ...

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How much do professional cadence design jobs pay per hour?

As of Aug 7, 2026, the average hourly pay for professional cadence design in the United States is $50.69, according to ZipRecruiter salary data. Most workers in this role earn between $39.18 and $61.78 per hour, depending on experience, location, and employer.
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Senior Principal DFT Design Engineer

Cadence Design Systems Inc.

Austin, TX • On-site

$124K - $171K/yr

Full-time

Posted 10 days ago

Cadence Design Systems rating

9.0

Company rating: 9.0 out of 10

Based on 5 frontline employees who took The Breakroom Quiz

33rd of 242 rated software companies

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.

Requirements;

US citizenship preferred.

  • Prior 10-20 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
  • Should possess intimate knowledge of DFT insertion flows
  • Basic scan chain insertion using synthesis or other software tools
  • Experience in compression scan insertion, LBIST and other scan technologies
  • Intimate knowledge of memory build-in self-test (MBIST)
  • Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
  • Debug and Analysis of failures to improve fault coverage
  • Verification of ATPG testbenches and debugging root cause of simulation mis-compares
  • Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
  • Knowledge of timing analysis and equivalency checks would be added bonus
  • Ability to work in collaborative team environment
  • Prior experience with Cadence tools and flows is highly desirable
  • Should be able to finish DFT tasks independently
  • Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems
  • Ability to work with stakeholders across cross-functional teams - Architecture, Design, Internal and External Customers
  • Self-driven and committed individual who can work in a fast-paced project environment
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