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Principal Mixed Signal Verification Engineer Jobs

Protingent

Mixed Signal Verification Engineer

San Jose, CA · On-site

$110 - $155/hr

Mixed Signal Verification Engineer Position Description : Protingent Staffing has an exciting contract Mixed Signal Verification Engineer with our client located in San Jose, CA. Job Responsibilities:

Retym

Mixed Signal Verification Engineer

Austin, TX · On-site

$134K/yr

Description For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Mixed signal verification engineer.

Apple

Mixed-Signal Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

Bodega Bay, CA · On-site

$175K - $308K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

Bodega Bay, CA · On-site

$122K - $214K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

Bodega Bay, CA

$175K - $308K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Apple

Mixed-Signal Verification Engineer

Bodega Bay, CA · On-site

$122K - $214K/yr

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the ...

Arago

Senior Mixed-Signal Verification Engineer

Paris, TX · On-site

$103K - $126K/yr

What you'll do As Senior Mixed-Signal Verification Engineer you will own the methodology, planning, and execution of mixed-signal verification for digital-to-analog interfaces on Arago's Systems-on ...

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Principal Mixed Signal Verification Engineer information

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$74K

$147.2K

$212.5K

How much do principal mixed signal verification engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for principal mixed signal verification engineer in the United States is $147,220.00, according to ZipRecruiter salary data. Most workers in this role earn between $118,500.00 and $173,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Principal Mixed Signal Verification Engineer jobs?

For Principal Mixed Signal Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Principal Mixed Signal Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 92% Full Time, 2% Part Time, and 6% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $147,220 per year, or $70.8 per hour.

Sr Principal Mixed Signal Verification Engineer

Richardson, TX • On-site

Qorvo, Inc.
Manufacturing • 5 - 10K employees
Learn more about Qorvo, Inc.external

Other

Re-posted 14 days ago

Qorvo rating

8.3

Company rating: 8.3 out of 10

Based on 21 frontline employees who took The Breakroom Quiz

Job description

Sr Principal Mixed Signal Verification Engineer

Experience Level: Professional

Job Type: Regular

Location: Richardson, TX 75081

Requisition ID: 10289

Responsibilities
  • Serve as customer-facing for catalog and custom power-management ICs including motor driver, power-loss protection, point of load, and battery management IC solutions.
  • Develop and execute metric-driven design verification plans based upon IC functional, performance, and test specifications, with a strong focus on the customer use-case.
  • Develop constrained random tests and automated checkers within our TLDV UVM environment.
  • Build high-performance, accurate RNM or VerilogAMS models to support TL simulation.
  • Collaborate with design team to resolve issues identified during verification.
  • Partner with internal design and test teams to ensure device first-pass testability.
  • Continuously improve and align verification methodologies with industry best practices.
  • Automate verification tasks where applicable.
Required Qualifications
  • Bachelor’s degree in electrical engineering or a related field, with strong focus on mixed-signal circuit design and verification.
  • 15+ years of experience or an equivalent amount of advanced education and experience in AMS design or verification of analog and power-management ICs.
  • Proficiency in UVM environments, including test cases, coverage models, and global checkers.
  • In-depth knowledge of power-management building blocks such as LDO, amplifiers, bandgaps, DCDC regulators, oscillators, and asynchronous state machines.
  • Excellent problem‑solving and debugging skills.
  • Effective communication and collaboration skills.
  • Expertise in mixed-signal concepts such as Spice/Spectre and event-based simulator, co-simulation environment, simulation debug, silicon debug.
Preferred Qualifications
  • Master’s degree in electrical engineering or a related field, with strong focus on mixed-signal circuit design and verification.
  • Experience in Top-Down Design Methodology.
  • Proficiency in shell or Python scripting.
  • Familiarity with SV-UDN/EENET modeling techniques.
  • Experience with both GUI and command-line simulation flows.
  • Proficiency with SV Assertions and Functional coverage.
  • Understanding integration of AI into a verification workflow.
Other
  • 10% or less domestic or international travel may be required.

We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.

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