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Post Silicon Test Engineer Jobs (NOW HIRING)

indie

Analog & DevOps ATE Test Engineer

Aliso Viejo, CA · On-site

... Test Engineer to own the development, validation, and productization of test solutions for our ... Support silicon bring-up and post-silicon validation, including handler and load board bring-up ...

Advanced Micro Devices

THE ROLE: AMD is seeking a Product Development Engineer to help deliver high-quality ... post-silicon debug, yield improvement, and manufacturing test-flow optimization. Working closely ...

indie

Analog ATE Test Engineer

Aliso Viejo, CA · On-site

Support silicon bring-up and post-silicon validation, including handler and load board bring-up ... Analyze engineering test data and report results to the team (design, product engineering ...

Amazon

Post Silicon Engineer, Amazon LEO

Austin, TX · On-site

The Post Silicon Engineer will play a pivotal role in a team that brings up, validates and ... Define, Design and Bring Up SOC Test Platforms. Own test automation and test benches, for ...

Google Inc.

Staff ATE Test Engineer

Sunnyvale, CA · On-site

As a Staff Engineer, you will set the technical direction for test coverage and quality standards ... post-silicon testing. * Oversee and optimize the chip production life-cycle, driving continuous ...

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Post Silicon Test Engineer information

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How much do post silicon test engineer jobs pay per hour?

As of Sep 10, 2026, the average hourly pay for post silicon test engineer in the United States is $44.24, according to ZipRecruiter salary data. Most workers in this role earn between $33.41 and $52.40 per hour, depending on experience, location, and employer.

What is the difference between Post Silicon Test Engineer vs ASIC Test Engineer?

AspectPost Silicon Test EngineerASIC Test Engineer
CredentialsBachelor's or Master's in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering or Computer Engineering
Work EnvironmentPost-production testing, debugging hardware, validating silicon chipsDesign verification, pre-silicon testing, simulation, and validation
Industry UsageSemiconductor companies, hardware firms, post-manufacturing phase

Post Silicon Test Engineers focus on testing and validating chips after manufacturing, ensuring functionality and performance. ASIC Test Engineers primarily work during the design phase, verifying chip designs before fabrication. Both roles require similar technical skills and educational backgrounds but differ in their project stages and responsibilities.

What cities are hiring for Post Silicon Test Engineer jobs?

Cities with the most Post Silicon Test Engineer job openings:

What are popular job titles related to Post Silicon Test Engineer jobs?

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Infographic showing various Post Silicon Test Engineer job openings in the United States as of September 2026, with employment types broken down into 1% As Needed, 83% Full Time, 13% Part Time, and 3% Contract. Highlights an 93% Physical, 2% Hybrid, and 5% Remote job distribution, with an average salary of $92,027 per year, or $44.2 per hour.

Principal Post-Silicon Validation Engineer

San Jose, CA • On-site

SambaNova
See more jobs at SambaNovaexternal

Full-time

Posted 23 days ago

Job description

About the team

We're the team behind post-silicon bring-up, debug, and validation for the high-speed IO and memory subsystems in SambaNova's DataScale platform. We own the path from first silicon power-on through field deployment: characterization, stress testing, performance validation, and root-causing issues across silicon, board, and software. We work directly with design, firmware, verification, and system engineering to keep bring-up on schedule, and partner with customer engineering on deployment and RMA debug. We build our own debug tooling and automation, and apply what we learn to pre-silicon verification to improve coverage on future programs.

About the role

SambaNova is seeking a Principal Engineer to own post-silicon bring-up, debug, and validation of high-speed IO and memory subsystems within the DataScale platform. This role is central to delivering reliable, high-performance AI systems at scale. You'll lead system-level debug across silicon, board, and software layers, driving issues to root cause from first silicon through field deployment. This is a hands-on role for an engineer with deep expertise in high-speed interfaces and hardware debug, who can operate in ambiguity and execute with high ownership.

Responsibilities
  • Own post-silicon bring-up and validation of high-speed IO and memory subsystems, spanning characterization, functional validation, stress testing, and performance analysis
  • Establish power-on readiness ahead of first silicon, including debug infrastructure, tooling, and contingency planning
  • Lead system-level debug to root cause complex issues spanning silicon, board, and software layers
  • Drive resolution with design, firmware, verification, and system teams to close issues and keep bring-up on schedule
  • Partner with system and customer engineering teams on product validation, deployment, and RMA debug
  • Own validation sign-off for product release against stability, performance, and field reliability targets
  • Review SoC and board design and SI/PI analysis through a post-silicon debug and deployment lens
  • Contribute to pre-silicon verification and emulation to improve bring-up efficiency and coverage
  • Build scripts and tooling that automate validation, debug, and data analysis, and scale test coverage across systems
  • Advance post-silicon validation methodology and debug infrastructure across programs
Required qualifications
  • M.S. in Electrical Engineering, Computer Science, or a related field
  • 7+ years of experience in post-silicon validation or system bring-up
  • Experience with two or more high-speed IO or memory protocols such as PCIe, Ethernet, HBM, CXL, or UCIe
  • Proven ability to lead cross-functional debug efforts to root cause and closure
  • Strong analytical skills for test development and data analysis
  • Proficiency in scripting such as Python and bash
  • Clear and effective communicator with a proactive, collaborative approach to problem-solving
Preferred qualifications
  • Deep understanding of high-speed SerDes training and adaptation
  • Experience with mixed-signal IO design and validation
  • Hands-on lab experience with oscilloscopes, protocol analyzers, and BERTs
  • Experience with optical interconnect
  • Ability to read and debug C/C++
 

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