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Post Silicon Characterization Engineer Jobs (NOW HIRING)

$53K - $68K/yr

Role Overview We are seeking an experienced Memory Quality and Reliability Engineer to drive post-silicon memory characterization, certification, and technology readiness activities for advanced SRAM ...

TD Memory Quality and Reliability Engineer

Folsom, CA · On-site

$77K - $99K/yr

Role Overview We are seeking an experienced Memory Quality and Reliability Engineer to drive post-silicon memory characterization, certification, and technology readiness activities for advanced SRAM ...

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Basic knowledge of post-silicon validation, characterization, qualification and manufacturing for ...

The Post Silicon Engineer will play a pivotal role in a team that brings up, validates and ... Key job responsibilities Define, Own and maintain Validation/Characterization plan for MODEM SOC ...

The Post Silicon Engineer will play a pivotal role in a team that brings up, validates and ... Key job responsibilities Define, Own and maintain Validation/Characterization plan for MODEM SOC ...

Silicon Validation Engineer

Cupertino, CA · On-site

$150K - $225K/yr

... characterization and validation. Design and implement data warehousing, visualization, and post ... and silicon characterization workflows. Develop artificial intelligence and machine learning ...

Silicon Validation Engineer

Cupertino, CA · On-site

$150K - $225K/yr

... characterization and validation. Design and implement data warehousing, visualization, and post ... Utilizing programming and scripting languages, including Python, C and Tcl, to develop, optimize ...

Silicon Validation Engineer

Cupertino, CA · On-site

$150K - $225K/yr

... characterization and validation. Design and implement data warehousing, visualization, and post ... Utilizing programming and scripting languages, including Python, C and Tcl, to develop, optimize ...

The Post Silicon Engineer will play a pivotal role in a team that brings up, validates and ... Key job responsibilities • Define, Own and maintain Validation/Characterization plan for MODEM ...

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Post Silicon Characterization Engineer information

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$108K

$172K

How much do post silicon characterization engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for post silicon characterization engineer in the United States is $107,956.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,500.00 and $133,500.00 per year, depending on experience, location, and employer.

What is a post silicon characterization engineer?

A Post Silicon Characterization Engineer is a professional who tests and analyzes semiconductor chips after they have been manufactured (post-silicon) to ensure they meet design specifications and performance targets. They develop test plans, run experiments on actual silicon, and work closely with design, validation, and manufacturing teams to identify and resolve issues. Their work is crucial for optimizing chip performance, ensuring reliability, and enabling successful product launches. This role often involves using specialized test equipment, data analysis tools, and deep knowledge of both hardware and software.

What are the key skills and qualifications needed to thrive as a post silicon characterization engineer?

To thrive as a Post Silicon Characterization Engineer, you need a strong background in electrical engineering, experience with silicon validation, and proficiency in data analysis, typically supported by a relevant degree. Familiarity with lab measurement equipment, scripting languages (like Python or Perl), and tools such as oscilloscopes and logic analyzers is essential. Excellent problem-solving skills, attention to detail, and effective communication help you collaborate with cross-functional teams and address complex silicon issues. These competencies are crucial for ensuring that silicon products meet performance specifications and for identifying and resolving issues prior to mass production.

What are typical challenges faced by a post silicon characterization engineer when validating new hardware designs?

Post Silicon Characterization Engineers often encounter challenges such as debugging unexpected hardware behavior, managing incomplete or evolving specifications, and working with limited documentation for new silicon. They must collaborate closely with design, test, and software teams to identify root causes of issues and develop effective test plans. The fast-paced environment and need for rapid problem-solving can be demanding, but it also offers opportunities to work on cutting-edge technology and directly influence product quality.

What does a post silicon characterization engineer do?

A post silicon characterization engineer tests and analyzes the performance of fabricated silicon chips to ensure they meet design specifications. They use specialized equipment and measurement tools to evaluate parameters such as power, speed, and reliability, often working closely with design and manufacturing teams to identify and troubleshoot issues. This role requires knowledge of semiconductor devices, test methodologies, and data analysis skills.

What are popular job titles related to Post Silicon Characterization Engineer jobs?

For Post Silicon Characterization Engineer jobs, the most frequently searched job titles are:

Infographic showing various Post Silicon Characterization Engineer job openings in the United States as of September 2026, with employment types broken down into 1% As Needed, 81% Full Time, 14% Part Time, and 4% Contract. Highlights an 92% Physical, 2% Hybrid, and 6% Remote job distribution, with an average salary of $107,956 per year, or $51.9 per hour.

Principal Post-Silicon Validation Engineer

San Jose, CA • On-site

$180K - $255K/yr

Full-time

Medical, Dental, Vision, Life

Posted 25 days ago


Key responsibilities

  • Own post-silicon bring-up, debug, and validation of high-speed IO and memory subsystems within the DataScale platform.

  • Lead system-level debug efforts to identify and resolve issues across silicon, board, and software layers, ensuring successful product deployment.

  • Develop and automate validation, debug, and data analysis tools and scripts to improve bring-up efficiency and test coverage.


Job description

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) - a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.
About the team
We're the team behind post-silicon bring-up, debug, and validation for the high-speed IO and memory subsystems in SambaNova's DataScale platform. We own the path from first silicon power-on through field deployment: characterization, stress testing, performance validation, and root-causing issues across silicon, board, and software. We work directly with design, firmware, verification, and system engineering to keep bring-up on schedule, and partner with customer engineering on deployment and RMA debug. We build our own debug tooling and automation, and apply what we learn to pre-silicon verification to improve coverage on future programs.
About the role
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SambaNova is seeking a Principal Engineer to own post-silicon bring-up, debug, and validation of high-speed IO and memory subsystems within the DataScale® platform. This role is central to delivering reliable, high-performance AI systems at scale. You'll lead system-level debug across silicon, board, and software layers, driving issues to root cause from first silicon through field deployment. This is a hands-on role for an engineer with deep expertise in high-speed interfaces and hardware debug, who can operate in ambiguity and execute with high ownership.
Responsibilities
  • Own post-silicon bring-up and validation of high-speed IO and memory subsystems, spanning characterization, functional validation, stress testing, and performance analysis
  • Establish power-on readiness ahead of first silicon, including debug infrastructure, tooling, and contingency planning
  • Lead system-level debug to root cause complex issues spanning silicon, board, and software layers
  • Drive resolution with design, firmware, verification, and system teams to close issues and keep bring-up on schedule
  • Partner with system and customer engineering teams on product validation, deployment, and RMA debug
  • Own validation sign-off for product release against stability, performance, and field reliability targets
  • Review SoC and board design and SI/PI analysis through a post-silicon debug and deployment lens
  • Contribute to pre-silicon verification and emulation to improve bring-up efficiency and coverage
  • Build scripts and tooling that automate validation, debug, and data analysis, and scale test coverage across systems
  • Advance post-silicon validation methodology and debug infrastructure across programs
Required qualifications
  • M.S. in Electrical Engineering, Computer Science, or a related field
  • 7+ years of experience in post-silicon validation or system bring-up
  • Experience with two or more high-speed IO or memory protocols such as PCIe, Ethernet, HBM, CXL, or UCIe
  • Proven ability to lead cross-functional debug efforts to root cause and closure
  • Strong analytical skills for test development and data analysis
  • Proficiency in scripting such as Python and bash
  • Clear and effective communicator with a proactive, collaborative approach to problem-solving
Preferred qualifications
  • Deep understanding of high-speed SerDes training and adaptation
  • Experience with mixed-signal IO design and validation
  • Hands-on lab experience with oscilloscopes, protocol analyzers, and BERTs
  • Experience with optical interconnect
  • Ability to read and debug C/C++

Base Salary Range:
Base Pay Range
$180,000-$255,000 USD
Submission GuidelinesPlease note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified.
EEO PolicySambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.
Benefits Summary for US-Based, Full-Time Employment Positions
SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.