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Post Silicon Characterization Engineer Jobs (NOW HIRING)

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Irvine, CA

$145K - $175K/yr

... post-silicon bringup and also help with ATE debug through all cycles of silicon characterization ... Bachelor's degree in electrical engineering, computer engineering, or physics * 5+ years of ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Sunnyvale, CA

$155K - $185K/yr

... post-silicon bringup and also help with ATE debug through all cycles of silicon characterization ... Bachelor's degree in electrical engineering, computer engineering, or physics * 5+ years of ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Irvine, CA · On-site

$145K - $175K/yr

SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... post-silicon bringup and also help with ATE debug through all cycles of silicon characterization

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Austin, TX · On-site

... post-silicon bringup and also help with ATE debug through all cycles of silicon characterization ... Bachelor's degree in electrical engineering, computer engineering, or physics * 5+ years of ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Irvine, CA · On-site

$145K - $175K/yr

... post-silicon bringup and also help with ATE debug through all cycles of silicon characterization ... Bachelor's degree in electrical engineering, computer engineering, or physics * 5+ years of ...

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Sunnyvale, CA · On-site

$155K - $185K/yr

SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... post-silicon bringup and also help with ATE debug through all cycles of silicon characterization

Qualcomm

DDR Bench Characterization Engineer

San Diego, CA · On-site

$131K - $173K/yr

This position is for the Post Silicon Engineering group that develops test solutions for highly ... Responsibilities include developing and executing characterization plans for High Speed IPs to ...

Phizenix

Staff DFT Engineer

Santa Clara, CA · On-site

... Post-silicon experience, including:Pattern bring-up and debug Silicon characterization and yield learning Experience mentoring junior engineers or owning DFT scan signoff

OMNIVISION

Design Characterization Engineer

Irvine, CA · On-site

$110K - $140K/yr

Bring up new silicon and validate CMOS image sensor functionality and performance in partnership with design engineers * Develop and refine characterization methodologies to evaluate image sensor ...

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Post Silicon Characterization Engineer information

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How much do post silicon characterization engineer jobs pay per year?

As of Jun 6, 2026, the average yearly pay for post silicon characterization engineer in the United States is $107,956.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,500.00 and $133,500.00 per year, depending on experience, location, and employer.

What are typical challenges faced by a Post Silicon Characterization Engineer when validating new hardware designs?

Post Silicon Characterization Engineers often encounter challenges such as debugging unexpected hardware behavior, managing incomplete or evolving specifications, and working with limited documentation for new silicon. They must collaborate closely with design, test, and software teams to identify root causes of issues and develop effective test plans. The fast-paced environment and need for rapid problem-solving can be demanding, but it also offers opportunities to work on cutting-edge technology and directly influence product quality.

What are the key skills and qualifications needed to thrive as a Post Silicon Characterization Engineer, and why are they important?

To thrive as a Post Silicon Characterization Engineer, you need a strong background in electrical engineering, experience with silicon validation, and proficiency in data analysis, typically supported by a relevant degree. Familiarity with lab measurement equipment, scripting languages (like Python or Perl), and tools such as oscilloscopes and logic analyzers is essential. Excellent problem-solving skills, attention to detail, and effective communication help you collaborate with cross-functional teams and address complex silicon issues. These competencies are crucial for ensuring that silicon products meet performance specifications and for identifying and resolving issues prior to mass production.

What is a Post Silicon Characterization Engineer?

A Post Silicon Characterization Engineer is a professional who tests and analyzes semiconductor chips after they have been manufactured (post-silicon) to ensure they meet design specifications and performance targets. They develop test plans, run experiments on actual silicon, and work closely with design, validation, and manufacturing teams to identify and resolve issues. Their work is crucial for optimizing chip performance, ensuring reliability, and enabling successful product launches. This role often involves using specialized test equipment, data analysis tools, and deep knowledge of both hardware and software.
Infographic showing various Post Silicon Characterization Engineer job openings in the United States as of May 2026, with employment types broken down into 1% As Needed, 91% Full Time, 1% Part Time, and 7% Contract. Highlights an 93% Physical, 3% Hybrid, and 4% Remote job distribution, with an average salary of $107,956 per year, or $51.9 per hour.
Sr. ASIC DFT Engineer (Silicon)

Sr. ASIC DFT Engineer (Silicon)

SpaceX

Irvine, CA

$145K - $175K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 7 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

13th of 59 rated aerospace companies

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. ASIC DFT ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
  • Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
  • Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
  • Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
  • Run and debug non-timing and SDF annotated gate-level simulations
  • Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization
  • Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C++

BASIC QUALIFICATIONS:
  • Bachelor's degree in electrical engineering, computer engineering, or physics
  • 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing

PREFERRED SKILLS AND EXPERIENCE:
  • Master's or PhD in electrical engineering, computer engineering, physics, or related engineering field
  • Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs
  • Hands-on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug
  • Experience collaborating with cross-functional teams (e.g., design, verification, and manufacturing) to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows
  • Knowledge of industry standards for testability (e.g., IEEE 1500, 1687) and experience with low-power DFT techniques using Siemens Tessent
  • Experience with In-System Test (IST), boundary scan (IEEE 1149.1), functional testing in embedded systems, or board-level diagnostics, preferably using Siemens Tessent tools
  • Hands-on experience with Tessent Streaming Scan Network
  • Experience with cell-aware fault models in ATPG
  • Excellent problem-solving skills, with the ability to analyze complex test failures and implement corrective actions
  • Strong communication skills for documenting test strategies, reporting results, and presenting to stakeholders
  • Ability to work in a fast-paced environment, handling multiple projects and adapting to evolving technology nodes (e.g., 7nm and below)

ADDITIONAL REQUIREMENTS:
  • Ability to work extended hours and weekends as needed to meet critical milestones
COMPENSATION AND BENEFITS:
Pay Range:
Level 1: $125,000 - $150,000
Level 2: $145,000 - $175,000
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.
ITAR REQUIREMENTS:
    Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to

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