1

Physical Design Engineer Internship Jobs in Texas

As part of our Silicon Engineering group, you'll help design and manufacture our next-generation ... An internship or prior work experience in timing closure or physical design. Experience working ...

Staff Physical Design Engineer

Austin, TX · On-site

$100K - $500K/yr

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from ...

Physical Design Engineer, PnR

Austin, TX · On-site

$100K - $500K/yr

Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions for an industry-leading AI SOC. You'll own the complete implementation flow from synthesis to ...

Participate in the development and improvement of physical design methodologies and flow automation. Minimum Qualifications * Bachelor's in Computer Engineering or Electrical Engineering or related ...

GPU Physical Design Engineer

Austin, TX

$134K - $138K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

GPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate cross-disciplinary ...

GPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

Physical Design Methodology CAD Engineer

Austin, TX · On-site

$134K - $138K/yr

... internships Exposure to CAD Tool, CAD flow or PD methodology. Understanding of some of the analysis involved in Physical Design - extraction, timing, noise, physical verification, EMIR.

GPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

GPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

GPU Top Level Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

Description As a GPU Top Level Physical Design engineer, you will collaborate with FE team to understand RTL and drive physical aspects early in design cycle. You will drive innovation with the ...

Showing results 21-40

Physical Design Engineer Internship information

What is a physical design engineer internship?

Physical Design Engineer internships are opportunities for students or recent graduates to gain hands-on experience in the field of semiconductor design, focusing on the physical implementation of integrated circuits (ICs). Interns typically work alongside experienced engineers to learn about tasks such as floorplanning, placement, routing, timing analysis, and verification using industry-standard Electronic Design Automation (EDA) tools. These internships provide exposure to the complete chip design flow, allowing interns to apply their knowledge of digital design and learn about key challenges in transforming logical circuit designs into manufacturable silicon. The experience is highly valuable for those seeking a career in VLSI or hardware engineering.

What do physical design engineer interns do?

As a Physical Design Engineer intern, you’ll typically assist with tasks such as floorplanning, placement, clock tree synthesis, and routing for integrated circuit (IC) designs. You may also help analyze timing, power, and area, supporting senior engineers in optimizing chip layouts. Interns often use industry-standard EDA tools and collaborate closely with teams in RTL design and verification. This hands-on experience allows you to develop your technical skills while gaining insight into the collaborative workflow of semiconductor design.

What are the key skills and qualifications needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid understanding of digital circuit design, VLSI concepts, and coursework in electrical or computer engineering. Familiarity with EDA tools like Cadence, Synopsys, or Mentor Graphics, along with knowledge of scripting languages such as TCL or Python, is typically required. Strong analytical thinking, attention to detail, and effective communication skills help interns excel in team environments and complex problem-solving. These skills and qualifications are vital for ensuring accurate, efficient chip design and successful integration within engineering teams.

What is the difference between Physical Design Engineer Internship vs Digital IC Design Engineer?

AspectPhysical Design Engineer InternshipDigital IC Design Engineer
Required CredentialsTypically pursuing or recent graduate in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering, Computer Engineering, or related field
Work EnvironmentInternship setting within semiconductor or electronics companies, hands-on design tasksFull-time professional role, involved in digital circuit design and verification
Employer & Industry UsageUsed by semiconductor companies, chip design firms, and tech companies for trainingFull-time employment in similar companies, focusing on digital IC development

The Physical Design Engineer Internship provides hands-on experience in chip layout and physical implementation, often for students or recent grads. In contrast, the Digital IC Design Engineer role involves full-time digital circuit design and verification. Both roles are essential in semiconductor development, but internships serve as entry points for aspiring engineers to gain industry exposure.

What are the most commonly searched types of Physical Design Engineer jobs in Texas?

The most popular types of Physical Design Engineer jobs in Texas are:

What cities in Texas are hiring for Physical Design Engineer Internship jobs?

Cities in Texas with the most Physical Design Engineer Internship job openings:

Infographic showing various Physical Design Engineer Internship job openings in Texas as of August 2026, with employment types broken down into 6% Internship, 88% Full Time, and 6% Part Time. Highlights an 94% In-person, and 6% Remote job distribution.

Staff CPU Physical Design Engineer

Google Inc.

Austin, TX • On-site

$192 - $278/hr

Other

Posted 11 days ago


Google rating

8.8

Company rating: 8.8 out of 10

Based on 103 frontline employees who took The Breakroom Quiz

48th of 247 rated software companies


Job description

Share Staff CPU Physical Design Engineer



  • Copy link


Google Austin, TX, USA ; Mountain View, CA, USA
Advanced

Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders;deep expertise in domain.


Share Staff CPU Physical Design Engineer



  • Copy link


In most instances, this position requires in-person interviews as part of the hiring process. Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA.



  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

  • 10 years of experience in high-performance, low-power physical design implementation or design convergence techniques with custom or industry standard synthesis, PnR and signoff tools.


Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

  • Experience leading cross-functional engineering initiatives across Architecture, RTL, DFT, and Technology partners to optimize sub-system microarchitecture.

  • Understanding of power grid design, EMIR constraints, and low-power implementation techniques.

  • Track record of architecting CPU class physical design methodologies, custom tool enhancements, or AI/ML-assisted PPA optimization flows.


About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.


About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.


Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.


Individual pay is determined by factors including job-related skills, experience, and relevant education or training.


US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits


Learn more about benefits at Google.



  • Lead end-to-end physical design strategy and execution for top-level and critical CPU blocks across advanced process nodes.

  • Pioneer novel physical design methodologies, tool flows, and AI/ML optimization techniques to maximize power, performance, and area (PPA).

  • Resolve complex timing, power grid, electromigration and IR drop (EMIR), and physical verification bottlenecks in tight iteration loops.

  • Drive technical roadmaps, mentor executive engineering peers, and influence architectural trade-offs across cross-functional teams.


Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .


Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.


Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

#J-18808-Ljbffr

What Google employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom