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Physical Design Engineer Intern Jobs in San Rafael, CA

Droyd Robotics

Mechanical Engineer Intern

San Francisco, CA · On-site

$22 - $29.75/hr

About the Role As a Mechanical Engineering Intern at Droyd, you will work hands-on on real robotic ... a physical build * Are comfortable using modern CAD tools (Onshape preferred, but not required)

Droyd Robotics

Mechanical Engineer Intern

San Francisco, CA · On-site

$22 - $29.75/hr

About the Role As a Mechanical Engineering Intern at Droyd, you will work hands-on on real robotic ... a physical build * Are comfortable using modern CAD tools (Onshape preferred, but not required)

TenX Semi

Chip Design Engineer

San Francisco, CA · On-site

$140 - $210/hr

Physical design awareness (floor planning, clock tree, routing congestion). * Background in ... MS in Electrical Engineering or Computer Science. Why Join Us You will be at the forefront of AI ...

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All JobsPhysical Design Engineer Intern JobsPhysical Design Engineer Intern Jobs in San Rafael, CA

Physical Design Engineer Intern information

See San Rafael, CA salary details

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$32

How much do physical design engineer intern jobs pay per hour?

As of Sep 2, 2026, the average hourly pay for physical design engineer intern in San Rafael, CA is $21.53, according to ZipRecruiter salary data. Most workers in this role earn between $17.93 and $23.32 per hour, depending on experience, location, and employer.

What does a physical design engineer intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What skills and qualifications are needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a physical design engineer intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What cities near San Rafael, CA are hiring for Physical Design Engineer Intern jobs?

Cities near San Rafael, CA with the most Physical Design Engineer Intern job openings:

Physical Design Engineer Intern jobs near you
Infographic showing various Physical Design Engineer Intern job openings in San Rafael, CA as of August 2026, with employment types broken down into 1% As Needed, 75% Full Time, 21% Part Time, 2% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $44,783 per year, or $21.5 per hour.

Analog and Mixed-Signal IC Design Engineer Intern

Neuralink

South San Francisco, CA

$35/hr

Internship

Re-posted 15 days ago

Job description

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. To accelerate our pathway to human ready brain-computer interfaces, you will have the opportunity to partner with our electrical, microfabrication, chip designers, neuro and mechanical engineers.

Job Responsibilities:

We are looking for Analog and Mixed-Signal IC Design Engineer Interns who are interested in architecting and implementing innovative solutions with high energy-efficiency and compact silicon footprint and who thrive with the autonomy to propose creative approaches to problems. 

Neuralink strives to be, as much as possible, a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals with different skill sets and perspectives, and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us.

The Analog and Mixed-Signal IC Design Engineer Intern will be responsible for analog and mixed-signal chip design, from circuit design to layout and verification. 

  • Define and implement innovative and optimal analog and mixed signal circuit architectures and transistor-level circuit solutions to achieve a variety of challenging noise, mismatch, distortion, power consumption, and cost requirements
  • Defines verification plan for a portion of IP or chip and runs complex simulations and analyses (e.g., power, performance, linearity, yield) on designs
  • Designs, programs, and runs complex tests and reviews tests of other team members; ensures bugs and other issues are identified and appropriately analyzed

Key Qualifications:

  • Minimum 1 years of experience in analog/mixed-signal integrated CMOS circuit design for a specific area (e.g., delta-sigma ADC, SAR ADC, DAC, VCO, PLL, DLL, Audio CODEC and Class D audio amplifier, high speed PHY & SERDES) with a successful track record of silicon validation
  • Minimum 3 months experience of application of technical skills outside of the classroom (examples: laboratory, research, extracurricular project teams, open source contributions, volunteering, personal projects or prior internship/work experience)
  • The ideal candidates are people who get excited about building things, are highly analytical, and enjoy tackling new problems regularly

Preferred Qualifications:

  • Skills in scripting and automation for complex simulation scenarios
  • Experience in lab testing of high-precision analog and mixed-signal ICs
  • Functional modeling experience and logic verification with Verilog AMS and SystemVerilog
  • Experience in design and layout with advanced CMOS FinFET technologies
  • Experience with design for high-volume production

Pay Transparency:

Based on California law, the following details are for California individuals only:

California Hourly Rate:

$35/hr USD

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